Hi
I am doing a high speed design with the DS90UR916 and is experiencing some error with the ibis model in the simulation.
- while performing a driver analysis on the PCLK pin, there is a strange signal at the rising edge, which after checking with ibis syntax checker, warning of data is non-monotonic. Is there anyway of resolving this?
- pin 49/50 is NC and cannot be simulated. Is it possible to simulate the LVDS signals since now the RIN+/RIN- are not possible to be import in.
am also attaching the screen shot of the signal of PCLK as follows:
Regards
Lin Biao