DS110DF410 - ADR 0x02 : CDR Status

Currently,I am testing using the EVM, could you please confirm if my recognition is correct ?

- Bit7 : PPM Count met
I think, If this bit is "1" , PPM Count is inside the range of register setting ADR 0x60 to 0x64.
However, I see this bit set when there is no signal. What does this mean ?

Bit6 : Auto Adapt Complete
CTLE/DFE Adaaptation succeeded.

Bit5 : Fail Lock Check
I think this bit is set when the device is in false lock. I have never seen this bit set.

Bit4 : Lock
This bit seems to change at the same time with CDR Lock. What is the difference ?

Bit3 : CDR Lock
This bit seems to link with LOCK pin. You could monitor current lock status of CDR.

Bit2 : Single Bit Limit Reached
I have no idea.

Bit1 : Comp LPF High
Bit0 : Comp LPF Low
Monitoring Loopfilter voltage ?
These 2 bits are always "0" testing with my EVM.

Thanks and Best Regards,
Kawai

Kawai-San,

I am checking on this and will let you know.

Regards,,nasser

Kawai-San,

Please below note a description of these bits.

Please note some of these bits are periodically reseted by the state machine. So they may not have a constant or stable readings. If you read back this register when the lock has been stable, you will see mostly 0xDC, 0x9C, and very occasionally 0xD8 or 0x98. Please mainly concentrate on using bits 0x02[3] only.

Here are the definition of these bits:

CDR Status:

Bit 7: PPM Count Met

This bit is set when the device is locked and the ppm count is within the programmed ppm count registers(0x60 through 0x64)

Bit 6: Auto Adaptation Complete

This bit is set when CTLE adaptation is complete and transfer is passed to DFE adaptation.

Bit 5: Fail Lock check: This bit is set to indicate the rate is outside of the of the ppm count value

Bit 4: Lock

Bit 3: CDR Lock

These two bits are set when the device is locked. Lock bit can be over written to trick the device to think it is locked. But CDR Lock is the true lock indication. Bit 4 is used by the manufacturing ATE test program. Please note CDR Lock normally gets set after 0x02[6] gets set.

Bit 2: SBT: Single Bit Transition: This is used to average the arrival of the single bits to determine the bit rate.

Bit 1 and Bit 0: Internal loop filter comparator settings

Regards,,nasser

Nasser-san,

Could you please tell me a little bit more in detail for the following bits ?

Bit 2: Single Bit Limit Reached
When this is "1" what does this mean ?
Do you mean that the device have enough "1" and "0" transition in the input signal to determine the bit rate, which means good (normal) operation ?

Bit 1 and Bit 0: Comp LPF High/Low
When this is "1" what does this mean ?
When "1", is the device's LPF voltage (VCO control voltage) is in upper or lower edge which is about to lose lock ?

Best Regards,
Kawai