Hello everyone,
I was wondering if anyone else has come across an issue I am currently working through (and hopefully has a brilliant solution). I am working on using the LMH1983 to generate my audio/video clocks for 3G/HD/SD video and audio decoding. Currently I am configuring the LMH1983's TOF1 to start up in crash mode (both near and far configurations) in order to achieve faster locking. This works great with the exception of when the same reference is lost and re-attained (in this case the cable is being pulled and re-asserted). When the signal is lost the system will go into hold-over mode as expected with a small drop in drive voltage (I suspect due to the time it takes to recognize the signal was lost). When the signal is then re-asserted the LMH1983 re-lock process creates large video and audio glitches.
My current method for dealing with this involves keeping my start-up procedure, but as soon as I achieve lock I switch the chip into drift mode. While this works it does introduce a problem case involving the introduction of a new reference source different to the previous. I am providing my initial configurations in a attached file. If you see something that should be changed to allow for a smoother re-acquisition please let me know.
Note: If the reference is lost my system (FPGA) automatically suppresses the HVF signals to the LMH1983 as soon as the HSync input is lost. The software will not allow the HVF inputs to be re-enabled until a valid reference is applied. We are using the LMH1981 to generate the HVF signals. The LMH1981 HVF signals are routed through an FPGA to the LMH1983.
Thanks for any feedback,
J. Ryan Shore.
LMH1983 Shadow Contents
0x00 DEVICE_STATUS_REF
INTERLACED: 1 ANALOG_REF 1 INPUT_POLARITY: 0 HSYNC_STATUS 0 H_ONLY: 0 LOR_STATUS: 1 LOST_HSYNC: 0
0x01 DEVICE_STATUS_LOCK
Lock_Status: 1 Align_Status 0 Wrong_Format: 0 Holdover: 0
0x02 PLL_LOCK_OUTPUT_ALIGN_STATUS
Lock_PLL4: 1 Lock_PLL3 1 Lock_PLL2: 0 Lock_PLL1: 1 Align_PLL4: 0 Align_PLL3: 0 Align_PLL2: 0 Align_PLL1: 1
0x03 REVISION_ID
Revision_ID: 0xC0
0x04 RSVD_04 Reserved 0x0
0x05 DEVICE_CONTROL
Soft_Reset: 0 Powerdown: 0 EN_AFD: 1 PLL1_Mode: 1 LOR_Mode: 0 Force_148: 0 GOE: 1
0x06 INPUT_POLARITY
EN_AUOTPOL: 1 HIN_POL_OVR 0 VIN_POL_OVR: 0 FIN_POL_OVR 0
0x07 OUTPUT_MODE_PLL2_FORMAT
PLL2_Format: 14
0x08 OUTPUT_MODE_PLL3_FORMAT
PLL3_Format: 13
0x09 OUTPUT_MODE_MISC
AFS_Mode: 1 XPT_Mode: 3
0x0A OUTPUT_BUFFER_CONTROL
CLK_HIZ: 0x0 FOUT_HIZ: 0x0
0x0B OUTPUT_FRAME_CTL_OFFSET1_MSB TOF1_Offset_MSB: 0x0
0x0C OUTPUT_FRAME_CTL_OFFSET1_LSB TOF1_Offset_LSB: 0x0 Total: 0
0x0D OUTPUT_FRAME_CTL_OFFSET2_MSB TOF2_Offset_MSB: 0x0
0x0E OUTPUT_FRAME_CTL_OFFSET2_LSB TOF2_Offset_LSB: 0x0 Total: 0
0x0F OUTPUT_FRAME_CTL_OFFSET3_MSB TOF3_Offset_MSB: 0x4
0x10 OUTPUT_FRAME_CTL_OFFSET3_LSB TOF3_Offset_LSB: 0x64 Total: 1124
0x11 ALIGNMENT_CTL_TOF1
TOF1_Align_Mode: 0 TOF1_Sync_Near: 1 TOF1_Sync_Far: 1 TOF1_Sync_Slew: 0
0x12 ALIGNMENT_CTL_TOF2
TOF2_Align_Mode: 0 TOF2_INIT: 0
0x13 ALIGNMENT_CTL_TOF3
TOF3_Align_Mode: 0 TOF3_INIT: 0
0x14 ALIGNMENT_CTL_AFS
AFS_ALign_Mode: 3 AFS_Init_Input: 0 AFS_INIT: 0
0x15 LOSS_OF_ALIGNMENT_CTL
LOA_Window: 2
0x16 LOR_CTL_HOLDOVER_SAM_V_MSB VC_Hold_MSB: 0x2
0x17 LOR_CTL_HOLDOVER_SAM_V_LSB VC_Hold_LSB: 0x3 Total: 515
0x18 LOR_CTL_FREE_RUN_CTL_V_MSB VC_Free_MSB: 0x1
0x19 LOR_CTL_FREE_RUN_CTL_V_LSB VC_Free_LSB: 0xFF Total: 511
0x1A LOR_CTL_ADC_DAC_DISABLE
ADC_Disable: 0 DAC_Disable: 0
0x1B LOSS_OF_REF_THRESHOLD
HSYNC_Missing_Threshold: 0 LOR_Threshold: 6
0x1C LOSS_OF_LOCK_THRESHOLD
LOCK1_Threshold: 16
0x1D MASK_CTL_PLL_LOCK_OUTPUT_ALIGN
MASK_LOCK4: 0 MASK_LOCK3: 0 MASK_LOCK2: 0 MASK_LOCK1: 0
MASK_TOF4_ALIGN: 0 MASK_TOF3_ALIGN: 0 MASK_TOF2_ALIGN: 0 MASK_TOF1_ALIGN: 0
0x1E RESERVED_1E Reserved 0x0
0x1F RESERVED_1F Reserved 0x0
0x20 INPUT_FORMAT_LMH1983
Input_Format: 0
0x21 OUTPUT_FRAME_LOOKUP_INPUT_VSYNC_CODE
Input_Vsync_Code: 3
0x22 OUTPUT_FRAME_LOOKUP_PLL2_VSYNC_CODE
PLL2_Vsync_Code: 5
0x23 OUTPUT_FRAME_LOOKUP_PLL3_VSYNC_CODE
PLL3_Vsync_Code: 6
0x24 RESERVED_24 Reserved 0x0
0x25 PLL1_ADVANCED_CTL
PLL1_DIV: 0 PLL1_Input_Mode: 0 FastLock: 1
0x26 PLL1_ADVANCED_CTL_FASTLOCK_DELAY
FastLock_Delay: 2
0x27 PLL1_ADVANCED_CTL_FASTLOCK_CURR
FastLock_ChargePump_Current: 31
0x28 PLL1_ADVANCED_CTL_CHARGE_PUMP_CURR
PLL1_Charge_Pump_Current: 8
0x29 PLL1_ADVANCED_CTL_R_COUNTER_MSB R_CNT_MSB: 0x0
0x2A PLL1_ADVANCED_CTL_R_COUNTER_LSB R_CNT_LSB: 0x1 Total: 1
0x2B PLL1_ADVANCED_CTL_N_COUNTER_MSB N_CNT_MSB: 0x6
0x2C PLL1_ADVANCED_CTL_N_COUNTER_LSB N_CNT_LSB: 0xB4 Total: 1716
0x2D PLL1_ADVANCED_CTL_LOCK_STEP_SIZE
LOCK_STEP_SIZE: 8
0x2E PLL2_ADVANCED_CTL_MAIN
PLL2_DIV: 0 PLL2_DISABLE: 0
0x2F PLL2_ADVANCED_CTL_CHARGE_PUMP_CURR
ICP2: 2
0x30 PLL2_ADVANCED_CTL_VCO_RANGE
VCO_RNG2: 12
0x31 PLL3_ADVANCED_CTL_MAIN
PLL3_DIV: 0 PLL3_DISABLE: 0
0x32 PLL3_ADVANCED_CTL_CHARGE_PUMP_CURR
ICP3: 3
0x33 PLL3_ADVANCED_CTL_VCO_RANGE
VCO_RNG3: 5
0x34 PLL4_ADVANCED_CTL_MAIN
PLL4_DIV: 3 PLL4_DISABLE: 0 IS125M: 0 PLL4_Mode: 0
0x35 PLL4_ADVANCED_CTL_CHARGE_PUMP_CURR
ICP4: 8
0x36 PLL4_ADVANCED_CTL_R_COUNTER
DIV_R4: 75
0x37 PLL4_ADVANCED_CTL_N_COUNTER_MSB DIV_N4_MSB: 0x2
0x38 PLL4_ADVANCED_CTL_N_COUNTER_LSB DIV_N4_LSB: 0x0 Total: 512
0x39 PLL4_ADVANCED_CTL_VCO_RANGE
VCO4_Range: 22
0x3A LVDS_CONTROL
LVDS_Boost: 0 LVDS_DIF: 4 LVDS_CM: 9
0x3B TOF1_ADV_CONTROL_LPF_MSB TOF1_LPF_MSB: 0x2
0x3C TOF1_ADV_CONTROL_LPF_LSB TOF1_LPF_LSB: 0xD Total: 525
0x3D TOF2_ADVANCED_CTL_CPL_MSB TOF2_CPL_MSB: 0xA
0x3E TOF2_ADVANCED_CTL_CPL_LSB TOF2_CPL_LSB: 0x50 Total: 2640
0x3F TOF2_ADVANCED_CTL_LPF_MSB TOF2_LPF_MSB: 0x4
0x40 TOF2_ADVANCED_CTL_LPF_LSB TOF2_LPF_LSB: 0x65 Total: 1125
0x41 TOF2_ADVANCED_CTL_FRAME_RESET_MSB TOF2_RST_MSB: 0x2
0x42 TOF2_ADVANCED_CTL_FRAME_RESET_LSB TOF2_RST_LSB: 0x58 Total: 600
0x43 TOF3_ADVANCED_CTL_CPL_MSB TOF3_CPL_MSB: 0x8
0x44 TOF3_ADVANCED_CTL_CPL_LSB TOF3_CPL_LSB: 0x98 Total: 2200
0x45 TOF3_ADVANCED_CTL_LPF_MSB TOF3_LPF_MSB: 0x4
0x46 TOF3_ADVANCED_CTL_LPF_LSB TOF3_LPF_LSB: 0x65 Total: 1125
0x47 TOF3_ADVANCED_CTL_FRAME_RESET_MSB TOF3_RST_MSB: 0x0
0x48 TOF3_ADVANCED_CTL_FRAME_RESET_LSB TOF3_RST_LSB: 0x1 Total: 1
0x49 TOF4_ADVANCED_CTL_AFS
TOF4_AFS: 5
0x4A TOF4_ADVANCED_CTL_ACLK
TOF4_ACLK: 11
0x4B RESERVED_4B Reserved 0x0
0x4C RESERVED_4C Reserved 0x0
0x4D RESERVED_4D Reserved 0x0
0x4E RESERVED_4E Reserved 0x0
0x4F RESERVED_4F Reserved 0x0
0x50 RESERVED_50 Reserved 0x0
0x51 USER_AUTO_FORMAT_27M_HIGH_VAL_MSB USR_27M_High_MSB: 0x0
0x52 USER_AUTO_FORMAT_27M_HIGH_VAL_LSB USR_27M_High_LSB: 0x0 Total: 0
0x53 USER_AUTO_FORMAT_27M_LOW_VAL_MSB USR_27M_Low_MSB: 0x0
0x54 USER_AUTO_FORMAT_27M_LOW_VAL_LSB USR_27M_Low_LSB: 0x0 Total: 0
0x55 USER_AUTO_FORMAT_R_DIV_MSB USR_DIV_R1_MSB: 0x0
0x56 USER_AUTO_FORMAT_R_DIV_LSB USR_DIV_R1_LSB: 0x0 Total: 0
0x57 USER_AUTO_FORMAT_N_DIV_MSB USR_DIV_N1_MSB: 0x0
0x58 USER_AUTO_FORMAT_N_DIV_LSB USR_DIV_N1_LSB: 0x0 Total: 0
0x59 USER_AUTO_FORMAT_CHARGE_PUMP_CURR
USR_ICP: 0
0x5A USER_AUTO_FORMAT_LPF_MSB USR_TOF_LPF_MSB: 0x0
0x5B USER_AUTO_FORMAT_LPF_LSB USR_TOF_LPF_LSB: 0x0 Total: 0
0x5C USER_AUTO_FORMAT_AFS
USR_TOF4: 0
0x5D USER_AUTO_FORMAT_MISC
EN_USERMODE: 0 USR_IINTERLACED: 0 USR_IN_VS_CODE: 0