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DP83848 Malfunction After Sometime

Dong Lin Lee
Prodigy 30 points
Other Parts Discussed in Thread: DP83848I-MAU-EK

Hi all,

I used DP83848VVVBC which is sample requested from TI. I had four PCB board prototype which were populated with DP83848VVVBC as the ethernet physical chip. The MCU that I used is PIC32MX675F512H with Microchip TCP/IP stack. 

All the board were functioning at the beginning, but after one day, three of my boards were malfunction. I cannot detected the physical chip so I suspect the chip somehow malfunction, after I replace the DP83848, two of my boards were recovered. I did not go in deep to find out the problem because I think that this might be the soldering problem to cause these boards malfunction.

After two month, one of my board malfunction again and cannot detect the network chip. I doubt is that any design error that cause this to happen.

Here is my schematic and PCB layout file in Altium10. I hope someone can help me out to solve this problem.

Thanks and appreciate anyone to give me advices.

Donnie Lee

schematic & pcb.rar
  • 0
    TI__Mastermind 31600 points

    Donnie,

    A review of the schematic and layout is a good first step in understanding this issue.  Thank you for providing this data.  We will review the design and respond with any questions or comments.

    Patrick

  • 0 in reply to Patrick OFarrell
    Prodigy 30 points

    Hi Patrick,

    Thanks for your prompt response. Let me know if you need any more information to detect the problem.

    Many thanks.

    Donnie Lee

  • 0 in reply to Dong Lin Lee
    Prodigy 30 points

    Hi Patrick,

    The problem still haven resolve. One of my board never fail, but other will fail suddenly, and will recover after sometime(few months or few weeks), and then fail again and repeat again.

    When the chip fail, the PIC cannot detect the PHY chip. I read the register BMCR it return 0xFF. The SPEED LED also did not light up.

    Hope can get your help on this issue. THANKS.

    Donnie Lee

  • 0 in reply to Dong Lin Lee
    TI__Mastermind 31600 points

    Donnie,

    I think it will be best to break my feedback into four parts - symptoms of the problem, schematic, layout, and reference materials.

    Symptoms of the Problem:

    1. The nature of the problem is unclear to me.  Specifically, I do not understand what is done to cause the device to go from a failing condition to a normal operating condition and vice versa.  What is done to the board in the case where it "will recover after sometime (few months or few weeks)"?  Is the power cycled or a reset applied?  Is the board submitted for re-flow or is the device itself re-soldered?
    2. When the problem occurs, you noted that you "read the register BMCR it return 0xFF. The SPEED LED also did not light up."  Is this always the condition of the failure or are there other symptoms?

    Schematic:

    1. The schematic looks pretty good.  It is well organized and the connections look correct. 
    2. However, there are two points that I would like to highlight:
      1. The 3.3V supply for the PHY has multiple 0.1uF capacitors, but I would prefer to see one or two 10uF capacitors near the PHY as well.
      2. For the 50MHz reference clock and the RMII data signals, series terminations are often preferred in order to optimize the signal integrity. 

    Layout:

    I have several concerns with the layout.  Since I do not have a good understanding of the symptoms, it is not clear to me that they are the only or primary cause of the failing condition, but they could certainly be contributors.  My main concerns are:

    1. We typically recommend at least a 4 layer board in order to meet signal integrity.  This 2 layer design creates some difficulties for implementing the best practices defined in our documentation.
    2. Some of the supply and ground connections are implemented as signal traces.  Of particular concern are the connections for the PFBOUT and PFBIN pins.  With the connections that are implemented, this supply may not be operating correctly. 
    3. The connection of the MDI signals to the terminations and the magnetics will result in sub-optimal performance:
      1. These traces should be well matched traces routed as 50 Ohms single-ended or 100 Ohms differential. 
      2. The 50 Ohm terminations should be placed near the device and between the device and the magnetics.
      3. The MDI signals should be routed on a single layer.

    Reference Materials:

    1. We have a design and layout guide on-line (http://www.ti.com/lit/pdf/snla079).  This document highlights many of the recommendations I have called out above and some additional helpful guidelines.
    2. The evaluation board for the DP83848 is a good resource as a reference design.  It is also available on-line (http://www.ti.com/tool/dp83848i-mau-ek). 

    Please let me know if you have any questions. 

    Patrick