TLK10232 BSDL

Hi Jon,

I have attached the BSDL file for the TLK10232. On the MDIO, do you have a 2k pullup on the MDIO pin and are all of the port address bits set correctly?http://e2e.ti.com/cfs-file.ashx/__key/communityserver-discussions-components-files/138/6201.TLK10232_5F00_DOT6.bsdl

Best regards,

Matt

Matt,

I think the MDIO core I am using in the FPGA is not working right. There are things about the waveform that seem wrong. I'm going to write another one and see if I can get a response.

Regards,

Jon

I managed to get MDIO working after reducing the clock speed. I am have trouble with all of the serial stuff however. The datasheet mentions a TLK10232 bringup guide, but I cannot find it anywhere. Here is what I have going on, hopefully touching on the key points.

HS is attached to SFP+ optical modules.

LS is x8 3.125gbps to an FPGA.

AN_ENABLE has been set to 0

MODE_SEL = 0

ST = 0

Originally I had turned on shallow loopback to see if I could at least get lane alignment with my own sequence but this is not working. I left that alone for now as it could be an SI issue. I put an optical loopback cable on the transceivers and enabled PRBS generation and verification on HS. This works, no errors with any PRBS. Now without PRBS enabled, I don't seem to get any HS link status. Ie. CHANNEL_STATUS is 0x1003. Which is no HS_CHANNEL_SYNC. KR_PCS_STATUS_1 is 0x4 and KR_PCS_STATUS_2 is 0, This also happens if I connect the module to a separate 10gb ethernet card. Perhaps I am misunderstanding the expected behavior here. Any thoughts?

Thanks,

Jon Pry

At this point I've successfully run PRBS through all interfaces, through the optical module, and into the fpga fabric and back without error. Still the link status is confusing me. I can't seem to tell if the HS link is operational or not. The thing certainly does not seem to like my XAUI alignment pattern either. The biggest issue is that the data received by the fpga is strange outside of PRBS mode. It seems to just be a constant data 10'b0010111100 or some rotation thereof. My guess is that this is K28.0. Am I wrong to expect a XAUI alignment pattern? Is there something I should be doing differently to initialize the chip for this type of operation?

Hi Jon,

I am attaching the Bringup Procedures document referred to by the datasheet. For your settings, you can follow the 4th procedure for "KR using manual mode settings learned from Link Training". Since you are not using KR, you can skip ahead to the subsection "Set in KR manual mode with Auto Negotiation and Link Training Off".

The XAUI bus should periodically be sending the reserved /A/ columns (K28.3 on all four lanes simultaneously) - this is needed by the TLK10232 for lane alignment. If lane alignment does not complete, the device will never be able to send valid data.

8422.tlk10232_BringupProcedures_v1p1.pdf

Matt,

    Thanks for the document, it was very helpful. I was not issuing a datapath reset which is required for anything but PRBS to work. I have a new problem though. It seems once the datapath is operational I am seeing very high error rates. For example before issuing datapath reset I can send and receive PRBS31 on either side seemingly indefinitely without error. After reset though, I am seeing error rates of several thousand per second on HS using the same pattern. I suspected power problems at first, like somehow activating the datapath was causing more load and noise on the power distribution network. Also I can increase the error rate by increasing transmitter voltage swing. However I do not see much of a current draw increase after issuing datapath reset, and I have tried adding and removing decoupling capacitors which seems to have no statistically significant impact on the error rate. I believe the problem is in the RX path as the link partner is fine with the 10gbe packets I am sending, but connecting the link partners transmitter causes all kinds of HS_ERROR to start showing up.

    Is there a particular power rail that is most likely responsible for this? Also I was wondering if somehow the analog parameters on power up are not the ones indicated by MDIO, such that when the first datapath reset happens, all analog stuff ends up changing.

Thanks,

Jon Pry

I found this thread http://e2e.ti.com/support/interface/high_speed_interface/f/138/t/246911.aspx regarding short traces from SFP+ to the chip. I thought I should mention that my traces are < 1". I turned on HS_ENTRACK and the error rate has gone down by a factor of 100, but is still way to high. Is there some way to turn off rx equalization entirely? Or maybe take manual control of the taps?

Hi Jon,

Yes, it would be good to set HS_EQPRE to a value of '101' or '110' to see if this improves the error rate. Setting this value to '111' disables the equalizer.

There are a few other settings to play with to optimize the link, most of these are in the same register as HS_EQPRE. It is good to look at the effect of HS_ENTRACK, HS_CDRTHR, HS_CDRFMULT, HS_PEAK_DISABLE, and HS_H1CDRMODE. Also, it might be good to set HS_AGCCTRL to '10' or '11' (forces the attenuator off and on) to see if that helps. Since each link is different, we recommend sweeping the combinations of these parameters to optimize the settings - it would be good if you have an automated way of doing this, but you can also tune the receiver settings manually.

It sounds like you are on the right track. I hope tuning these settings helps to get you to zero errors.

Best regards,

Matt