ESD for ISO7231

Hi Jin,

I am not sure that I fully understand your question.

• Which pins are you applying the pulses to?
• What do you mean by “adding point: GND
• During this test are you sending and monitoring data on all the isolation channels?

To you question about the structure of the EN pin, there is an equivalent schematic diagram of the EN pin on page 14 of the datasheet. Have you looked at that yet?

If you could share a schematic of the system you are testing with information on which pins are receiving the pulses and where you are transmitting and monitoring that would help me be of more assistance. 

Thanks,

John

Hi John

The customer was adding the Pulse between the GND and IGND for 5 ~ 10 Minutes and then the current consumption of the device is increased up to over 100mA with continually. After turn-off to turn- on. the device was normal operated.

I am assuming that the impulse signal go through GND to VCC and makes internal ESD diodes be conducted.

How about my assuming on that?  

According to the customer, When the EN1 is Open or Pull up by resister, the problem is no more exsist.

Customer ask us to give a way which one(Open or Pull resisiter) is more stable to prevent it from operating abnomally.

I think that in this case, Open for EN1 is more safety. How about this?

Please give me your opions on that

Thanks

Hi Jin,

Thank you for the explanation and the schematic. I think that I understand the issue now. There are three conditions you are referring to:

1. Transients with the EN pin open: No issue
2. Transients with the EN pin tied to Vcc through resistor: No issues
3. Transients with the EN pin tied directly to Vcc: High current draw requiring power cycle to alleviate

Please let me know if I am wrong. I apologize I was not able to get to this today, I will try and speak with someone on the design team tomorrow.

Thanks,

John

Hi Jhon

Yes, You understood the situation very well refer to the 1 ~ 3 you mentioned.

I am waiting for the answers from you.

Thanks

Hi Jin,

We have two more questions:

• What is the impedance of the PV3.3 or IPV5 power supply? 
• Which side is latching up?

Our idea on what is happening are:

• If the power supply is not low impedance, the Vcc pin could be getting coupled up above the abs max causing the ESD cell to turn on.   Or the power supply could be collapsing with respect to its own ground causing the ESD cell at the EN pin to become forward biased in which case a ton of current will be injected into the device and likely cause latchup.  The second case would be the likely cause if the bypass capacitors are not placed close to the device or if the capacitor itself has a high ESR.

The option of tying the EN pin to Vcc through a resistor is the safest way to prevent latchup on a susceptible input pin.  The internal pullups on the enable pin are in order of 1M ohm, so the concern about floating these pins is that noise could couple to the pins and case the state to change.

If it is an option, we recommend connecting the EN-pins high via 4.7kΩ resistors to Vcc at both sides of the device, with the resistors as close to the EN-pins as possible. Also, the bypass caps should be as close as possible to Vcc. Below is a note on the landing patterns that should be used to ensure minimum mutual inductance of the capacitor and resistor placements.

Thanks,

John

Hi Jhon

I answer for the below questions.

• What is the impedance of the PV3.3 or IPV5 power supply?

          ==> I do not know because customer could not measure the impedance of Power. Furthmore, she never have

                  experience that impedance makes an effects on sysstem.

• Which side is latching up?

         ====> VCC1 side

According ot the customer, she has already produced their system so that OPEN state for EN is prefered to pull up resistor solution. As you know the way of controlling EN on the data sheet, Open and tied to Vcc Both of them recommned.

 Of course, if Pull up resistor for EN is more stable than the OPEN for EN, I recommned the customer to use the way of using Pull Up resistor for EN.

Please give me your opinion about this and the reason of recommendation.

Thanks

Hello Jhon

According to the customer, she followed the below application note to design PCB artwork.

It means that although follow the Application note of TI, there is unstable operation of ISO7231.

Can I understand although follow the below application, the device can be unstable operation under very highly nosie eviroment?

This is because, the customer is confused with your explanation because the application of the datasheet just gives OPEN, connected to Vcc and 2mm trace for EN. However, customer follow Vcc connected to EN but this is unstable now.

Finally, Is it right that Pull up is the best way fo imunity for Noise?

Thanks

Hello, Jason and Jhon

I appriciated with your good support.

Your support makes the customer understand how to design the device.

Thanks and Best Regards