DS110DF111 - No output at loopback output

Kawai-San,

I made a small change in your block diagram and this specifies how the device operated.

Please let me know if both CDRs are locked.

Regards,,nasser4760.Device Block Diagram and LoopBack.pdf

Nasser-san,

Thank you for the change in the block diagram.

In our customer evaluation, CDR is locked and they have correct output in the normal operation.(Signal from INA to OUTA and INB to OUTB, no loopback)

When they set to Loopback mode, they cannot get the correct output.

The difference from the normal operation is setting the following registers.

Control/Shared Register
ADDR 0x07 [1:0] = 0x06 ... Loopback INA to OUTB

Channel Register
ADDR 0x09 [5] = "1" ... Enable override Output MUX *
ADDR 0x1E [7:5] = 3'b 001 ... MUX is set to Retimed data *

* I've asked customer to add ADDR 0x09/0x1E setting, but there were no difference.

Looking at the DS110DF111 product folder, it seems there is no EVM for this device. But, if there is a test board, I appreciate if you could confirm the device operation.

Best Regards,
Kawai

Nasser-san,

In our customer evaluation, they could not get the correct loopback output in the register setting below.

    Shared Register 0x07 [1:0] = 0x2 (INA to OUTB, INB to OUTB)

.

But, they got the correct Loopback signal when setting the register as the following.

    Shared Regsiter 0x07 [1:0] = 0x3 (INA to OUTB, INB to OUTA)

.

It seems that the block diagram may be wrong.

Is the device inhibited to set the Shared Register 0x07 [1:0] = "0x1" or "0x2" ?

The device OUT_B seemed to have competing waveform of IN_A and IN_B when Register 0x07[1:0] set to "0x2" in our customer evaluation.

Best Regards,
Kawai

Kawai-San,

Please refer to the corrected block diagram that i had attached to this E2E Case. Shared register 0x07[1:0] should be equal to 0x03 so we would have INA to OUTB and INB to OUTA.

As it relates to the Register 0x07 = 0x1 or 0x2, we have to check to see if there is any contention or competing waveform as you suggested.

For now, please use Register 0x07 = 0x3 for the loop back and i will check into 0x07 = 0x1 or 0x2.

Regards,,nasser

Kawai-san,

I would just like to ensure this is production silicon.  This can be checked in the shared register address space.

REG 0x01[7:5] = 011

Thanks,

Lee

Nasser-san, Lee-san,

Thank you for your support.
We look forward to hearing from you soon.

We already have checked the register setting.
Device Revision is the same value with the datasheet.

  Shared Register ADDR 0x01[7:5] is "011"

Best Regards,
kawai

Hi Kawai-san,

The register should be defined as below.

To make both loopbacks occur at the same time write Register 07[1:0] = 11

I do not see either of the waveforms impacting the other.  I tried this in the lab with a 1.25 Gbps signal and 10.3125 Gbps signal and two oscilloscopes.

Regards,

Lee

Lee-san,

I apologize for my delay.

Thank you for testing on your evaluation board.

 I understood that you have tested Register 0x07[1:0] = 11.  Have you tried Register 0x07[1:0] = 01 or 10 ?

These setting will set the device as below.

 - input of channel A and B to output of channel A
 - input of channel A and B to output of channel B

Is the device permitted to set Register 0x07[1:0] = 01 or 10 ?

Best Regards,
Kawai

Kawai-san,

Yes I looked at all three loopback conditions. The device is permitted to set these register bits to a 00, 01, 10, or 11 pattern.

Regards,

Lee