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FCS Error with DP83865

Benjamin Wozniak
Prodigy 20 points
Other Parts Discussed in Thread: DP83865

Hello,

 we use the DP83865 on our custom embedded board and observe strange Frame Check Sequence Errors for long packets (>650 bytes). The error rate increases with the package size and packets over ~1200 bytes are completely affected (screenshots appended). We are not sure if our circuit design is incorrect and cause the problems, but the link is stable and small packets are transmitted without problems. It would be nice if someone can help us to identify/solve this problem.

 With best regards,

 Benjamin Wozniak

  • 0
    TI__Mastermind 31600 points

    Benjamin,

    It would be best to start with a review of the schematic.  If you are uncomfortable posting the schematic to the forum, please let me know and we will work out an alternative.

    Patrick

  • 0 in reply to Patrick OFarrell
    Prodigy 20 points

    Hi Patrick,

    thank you for your reply. Below you can see the schematic (I hope the resolution ok). The DP83865 is connected to the xilinx zynq XC7Z020. The zynq uses RGMII v2.0, while the phy is only supporting v1.3. Is it possible that this difference is the problem?

  • 0 in reply to Benjamin Wozniak
    Prodigy 50 points

    Hi Ben -

    Just a few things to check on the hardware side:

    1. Have you checked the signal integrity and timing for the RGMII signals?  Can you verify the timing with a "high" traffic load?
    2. Has there been a review of the PCB layout for these traces? 
    3. Are you crossing over any high frequency switching sources (e.g. switching node from other supplies)? 
    4. Do you have a continuous ground reference?
    5. Have you double checked all the pin connections against the datasheet? For example, according to the datasheet VDD_SEL_STRAP needs to be tied low to set VDD_IO = 2.5V. The note says do NOT pull high/low through a resistor.
    -Thomas