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Power-on sequencing question on the TI XIO2001 PCEe-to-PCI bridge

Art Leitherer
Prodigy 10 points
Other Parts Discussed in Thread: XIO2001

 

I have a specific power-on sequencing question on the TI XIO2001 PCEe-to-PCI bridge we are using that is unclear in the datasheet of course. 

Here it is if you happen to know the answer:

Question -  According to the XIO2001 datasheet (SCPS212F, May 2012) in Section 3.1.1 it says to turn on the 1.5V and 3.3V voltages before applying PCIR.   Is there an electrical reason why PCIR can’t be turned on before 1.5V and 3.3V (the PCI clamp voltage shouldn’t have anything to do with anything else in the part I wouldn’t think)?    Basically what we want to do is exactly what is shown in Section 3.1.1 and for power-down in Section 3.1.2 except we want to leave the PCIR voltage on all of the time.   According to the datasheet as long as PCIR is applied the XIO2001 can take the signals as the input voltage range is spec’d as “-0.5 to PCIR + 0.5V” … and this is stated independent of any other power rails (there is nothing on the PCI bus that depends on the 3.3V and 1.5V rails except for outputs … which will not be active on the XIO2001 when we power it down).   

Why? -- We would like to power the 3.3V and 1.5V power down in sleep states and leave the PCIR voltage on since there could be live (but inactive) signals on the PCI bus.   Because of the stated voltage sequencing requirements in the datasheet we would be unable to ever turn off the power to the bridge since the devices on the PCI side remain powered beyond our control (but inactive when held in reset).

Thanks,

  • 0
    TI__Guru* 76130 points

    Hello,

    The I/O cells inside our part cannot handle more than 5Vcore. This is the 3 reason why we suggest powering up PCIR after a delay, so that the voltage between the rails doesn’t exceed the limit.

    What you are looking for is the PCI terminals to be 5V failsafe which are not on the XIO2001.

    Regards.

  • 0 in reply to Elias Villegas M.
    Intellectual 345 points

    Elias,

    Your datasheet (section 7.2) says that PCIR can be 5V (4.75V to 5.25V).  

    It also says (Section 7.1) that the input voltage range on PCI signals can be from -0.5V to (PCIR+0.5V) implying no dependency on the 3.3V or 1.5V power to the XIO2001. 

    We aren't trying to supply more than 5V on PCIR.  So, I don't understand the response.  Can you read the original question again since I thought I made this clear (but I can't see my original question for some reason so I might not have)?

    Here is a simplified version of what we want to do:

    1.  Turn on 5V supply going to PCIR (i.e., PCIR = 5V) on the XIO2001 and to the PCI bus (PCI bus will be in reset so there will not be any activity on the signals but signals may be pulled up to 5V).  The 3.3V and 1.5V power on the XIO2001 is off.

    2.  Wait some undefined period of time.

    3.  Turn on the 3.3V and 1.5V power to the XIO2001

    4.  Release reset

    Can we or can't we do this and if not ... why?

    Thanks

     

  • 0 in reply to Bob Fitch
    TI__Guru* 76130 points

    Hello Bob,

    The PCIR rail does not power the I/O cells inside the XIO2001, it is just the clamp for the ESD circuits and for the PCI bus.

    However, the I/O cells inside the XIO2001 must have a voltage reference before the PCI terminals start "seeing" power on the PCI bus. The PCI terminals are not failsafe, so you can't have voltage on the PCI Bus with the XIO2001 powered-off.

    The terminals PCIR on the XIO2001 can have 5V even when the XIO2001 is powered-off, but the PCI terminals can not have voltage with the XIO2001 powered-off.

    Regards.

  • 0 in reply to Elias Villegas M.
    Intellectual 345 points

    Elias,

    Thanks for clearing that up.  We will leave the device powered all of the time to avoid any issues.

    The XIO2001 datasheet should be made clearer for this since it really does imply that the inputs are PCIR-voltage tolerant on the "PCI" signals.

    I think this case can be considered closed.

    Thanks,

    Bob F.