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TFP401 questions

Dan Wieland
Intellectual 2625 points
Other Parts Discussed in Thread: TFP401, TFP401A, DS90UR124

The TFP401 is used on the DVI-FPD-Link II (DS90UR905/906) demo platform.  A customer wants to send it low resolution video of 480x240 or 400x240.  Will the TFP401A have problems receiving DVI video of that resolution?

 

Also – does the TFP401A have any way to communicate over the EDID bus?  Need to be able to tell the DVI transmitter what the display resolution size is, via EDID.

  • 0
    TI__Guru* 76130 points

    Hello Dan,

    The TFP401 does not care about resolution, it only cares about pixel clock frequency. The TFP401 will work with any resolution with a pixel clock between 25MHz and 165MHz.

    For example, a resolution of 400x240 at 60fps will produce a pixel clock of about 7.25MHz so the TFP401 will not operate reliable at this resolution.

    Regarding the EDID question, the TFP401 is not involved on the EDID communication, the EDID information will flow directly from the Display to the graphics controller through the DDC lines.

    Regards.

  • 0 in reply to Elias Villegas M.
    Prodigy 65 points

    Greetings Elias,

    I am the customer that Dan made reference to.  From your reply, it does not sound as though the TFP401 will be sufficient for my application.

    I am trying to output a low resolution image (possibly as low as 400 x 240 @ 60Hz) from a PC to a display for demonstration purposes.  The display is expecting FPD Link II and has the DS90UR124 deserializer onboard.  The  DVI-DS90UR905_906 eval. board was recommended as it would provide a nice DVI interface to the computer and output FPD Link II from a chip backward compatible with the DS90UR124.

    Would you have another recommendation as to how this could be accomplished?

    Let me know if I need to clarify any points.

    Thank you.

  • 0 in reply to Heffalump
    TI__Guru* 76130 points

    Unfortunately I don't.

    All of our DVI receiver works from 25MHz to 165MHz. You may find something on the High-Speed forum at http://e2e.ti.com/support/interface/high_speed_interface/default.aspx

    Regards.

  • 0 in reply to Elias Villegas M.
    Prodigy 65 points

    Elias,

    What about a resolution such as 480i?  My understanding is that this resolution only warrants a pixel clock of about 13.5 MHz.  However, through the implementation of pixel repetition (every pixel is repeated) the pixel clock can be boost to 27 MHz which gets it over the 25 MHz threshold.  The TFP401 supports 480i, correct?  I could not find this stated explicitly but assume it is so because the datasheet says it supports all modern resolutions up to 1080p and WUXGA.

    If the TFP401 can support 480i, do you know how this is accomplished?  Does the TFP401 have to recognize the pixel repetition and cut out the extra pixels before it sends the signal on to the rest of the circuit?  Is the pixel clock output of the TFP401 as limited as the RxC input to the TFP401 (25 - 165 MHz)?

    Thank you.

  • 0 in reply to Heffalump
    TI__Guru* 76130 points

    Hello,

    The TFP401 is only a serializer, it does not recognize resolution and certainly it can not recognize that the pixels come repeated.

    The TFP401 will only take the TMDS inputs and de-serialize them into parallel bits, if the pixels come repeated then you will see these data repeated at the TFP's output as well.

    The TFP401 will not work with a pixel clock below 25MHz.

    Regards.