TSB81BA3D input level of "XI" pin

Ryuji

Guru 20090 points

Other Parts Discussed in Thread: CDC7005

Hello,

TSB81BA3D has XI pin for reference clock.

But, there is not electrical characteristics of VIH, VIL in the datasheet.

I found "1.8V CMOS level" only.

(1)

Could you please kindly let me know the VIH, VIL ?

(2)

Is absolute maximum rating of XI pin "−0.5 V to VDD + 0.5 V" ?

Best Regards,

Ryuji Asaka

over 11 years ago

0 Elias Villegas M. over 11 years ago

TI__Guru* 76130 points

Hello,

Those parameter are not typically specified on an oscillator input, it is the threshold level which is specified instead, in this case XI has a threshold level equal to one half of the voltage measured on PLLVDD_core; if PLLVDD_core is 1.8V the threshold level of XI will be 0.8V.

You can find an application note for crystal selection at the below link.

Regards.

http://e2e.ti.com/support/applications/high_reliability/f/30/p/165912/608498.aspx

0 Ryuji over 11 years ago in reply to Elias Villegas M.

Guru 20090 points

Hello Elias san,

Thank you for the information.

I checked the application note for crystal selection.

I can find threshold level of XI as half of the voltage on the PLLVDD_core.

I think that there is hysterisis for VIL and VIH.

Could I have the hysterisis level ?

If there isn't the data of hysterisis, should I consider hysterisis for design ?

Best Regards,

Ryuji Asaka

0 Ryuji over 11 years ago in reply to Ryuji

Guru 20090 points

Hello Elias san,

Could I have your reply please ?

Sorry for bothering you, but I wait your response...

Best Regards,
Ryuji Asaka

0 Ryuji over 11 years ago in reply to Ryuji

Guru 20090 points

Hello Elias san,

I'm sorry for my postiing again and again.

We can't have any XI input information without below?

Then , I will explain to our customer it. Thus, please kindly let me know above my understanding is correct or not.

http://e2e.ti.com/support/applications/high_reliability/f/30/p/165912/608498.aspx

Best Regards,
Ryuji Asaka

0 Elias Villegas M. over 11 years ago in reply to Ryuji

TI__Guru* 76130 points

Hello Ryuji,

I am still looking for this information, I will reply as soon as I get it.

Regards.

0 Ryuji over 11 years ago in reply to Elias Villegas M.

Guru 20090 points

Hello Elias san,

Thank you for your checking.

I wait your reply.

Best Regards,
Ryuji Asaka

0 Ryuji over 11 years ago in reply to Ryuji

Guru 20090 points

Hello Elias san,

Sorry for bothering you. We considered this issue.

I think that Reference Clock need ultra low jitter, thus XI pin can't use schmitt trigger I/O.

As a result XI pin's threshold is one-half of PLLVDDcore voltage only.

Is my understanding correct?

Best Regards,

Ryuji Asaka

0 Elias Villegas M. over 11 years ago in reply to Ryuji

TI__Guru* 76130 points

Hello,

Ryuji, yes, you can tell that to customer.

I will follow up this requirement of getting the VIH and VIL

Regards.

0 Ryuji over 11 years ago in reply to Elias Villegas M.

Guru 20090 points

Hello Elias san,

Thank you for the checking.

(1)

When can I have the VIH, VIL information ?

Our customer request VIH, VIL strongly... they don't use this device without VIH, VIL information.

Sorry for bothering you, but pleae kindly let me know your estimated time.

(2)

I found the some information for CMOS input.

TSB81BA3DPFP has other CMOS input pins. These device threshold is as below.

PC0, BMODE pins etc... : VIH=Vdd*0.7V, VIL=Vdd*0.2V,

Reset pin : VIH=Vdd0.6V, VIL=Vdd*0.3V

Vdd=3.3V

and I found the REF_in pin on the CDC7005 of the Clock Jitter Cleaner device.

Threshold voltage of the CDC7005 REF_in pin is 0.5*Vdd.

And have VIH(0.7*Vcc) and VIL(0.3*Vcc).

This is for your reference. I expect that these specifications adapt to TSB81BA3D.

Best Regards,

Ryuji Asaka

0 Elias Villegas M. over 11 years ago in reply to Ryuji

TI__Guru* 76130 points

Hello,

Can you post your email address, I have some numbers taken from a test program.

Regards.

0 Ryuji over 11 years ago in reply to Elias Villegas M.

Guru 20090 points

Hello,

thank you for the checking. please send below address.

asaka-r@clv.macnica.co.jp

best regards.

Ryuji Asaka

Because of the holidays, TI E2E™ design support forum responses will be delayed from Dec. 25 through Jan. 2. Thank you for your patience.

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TSB81BA3D input level of "XI" pin