Within the TUSB1210 datasheet it says the following about RESETB:
"When low, all digital logic (except 32 kHz logic required for power up sequencing) including registers are reset to their default values, and ULPI bus is tri-stated. When high, normal USB operation."
We are trying to test a board containing a TUSB1210, which has CS tied to VDDIO via 1k. Even if we drive RESETB low, it seems the TUSB1210 is still driving the ULPI interface according to the "PLL OFF" column of table 6-3. This is not what was expected based on the description of the RESETB pin, so is there something else that needs to be done to tri-state the ULPI bus? We cannot set CS low, so that is not an option, and the clock is not running.
Figure 5-1 seems to agree that the ULPI Bus is not tri-state when RESETB is asserted, because it shows DIR being driven whilst RESETB is low.
Can anyone provide any clarification on whether this is a documentation error, or there is something else we should be doing?
Thanks,
Rob
