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LMH0366 Reclock inline Issue

Rocky Chen
Expert 8810 points
Other Parts Discussed in Thread: LMH0303, LMH0384, LMH0366

Hi Expert

Our customer Eoptolink is debugging LMH0366, LMH0303, LMH0384. They reported issue of LMH0366.

Issue descriotion: When testing with SMPTE pattern (270M, 1.485G, 2.97G), with CDR in line, lock bit has been asserted. But eye diagram is much worse (more jitter, or even crashed eye diagram) when CDR is in line. After bypass the CDR, it’s much better and we can get clear eye diagram.

Attached document contains SCH, Registers Settings and Eye Diagram of CDR inline/bypass. I am still getting PCB laout design.

Please kindly help on:

1, how we can improve and if there is any problem with the design and configuration?

2, Another issue is the datasheet of LMH0366 is not very clear on register description, do we have more documents or app?

 

Thanks a lot. 

Best Regards,

Rocky Chen

SCH, RegSetting, EyeD.docx
  • 0
    TI__Expert 8810 points

    PCB Layot attached, pls help review them together.

    While, below are some new findings, looking forward you support in time. Thanks!

    1, We coducted some testing, found that using samller value of Capacitor of loopfilter, will make 3Gbps E.D better, can achieve the performence of CDR off more or less. But this is just a testing, we wonder to know the detail data such as LMH0366 intenal loop filter and his BW calculations. Otherwise, we can not ensure tunning the value of the Cap would not affect jitter performence at low speed 270M.

    2, We have not tune register settings, but confirmed SPI works well, also the LOCK bit asserted once CDR on. Also I do not find problm of customer reister configurations.

    3, Power supply is good.

     

    Best Regads

    Rocky Chen

     

    PCB Layout.docx