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PCB: can Unbalanced USB differential pair work?

Paul Singh
Expert 2750 points
Other Parts Discussed in Thread: OMAPL138

Hi,

We have met problems when routing differential USB pairs for the OMAPL138 processor.

We have followed the USB 2.0 standard to route differential pair with 90Ω differential impedance (upper sub-figure example). However there are two problems we cannot correct due to layout constraints:

1.    Because of the relative placement and orientation of the USB header to the processor (and its USB0_D_P and USB0_D_N pins), after having routed the differential pair very close to the header, we had to “twist” them 180 degree with a switching of the layer (see middle sub-figure). This is shown as the yellow differential pair (internal layer) suddenly twisted and emerges on the top layer. Because of the relative position of the two pins on the processor and the header, if we do not “twist” near the header we have to twist somewhere else midway, but this is unavoidable. Would this cause USB fail?

I was wondering that if this causes any problem to high-speed USB communication, can we solve it by lowering USB clock speed, particularly when acting as the USB host?

2.    Near the processor there is a length of routing where we cannot parallel the two lines, and this corresponds to what is called “Max Uncoupled Length” by the Protel software (see the bottom sub-figure). How much “uncoupled length” is allowed by the USB 2.0 standard?

3.    The final differential pair is not perfectly balanced as shown in the left (panel) of the image in the USB0_D_P is 50mil shorter than USB0_D_N. Can the USB lines still work in this case? If problems encountered when acting as USB host, can we also solve this by lowering USB clock?

 

Paul

  • 0
    TI__Guru* 76130 points

    Hello Paul,

    Yes, those mismatches will cause issues.

    The total trace length mismatch should be less than 5 mils, we usually do less than 3 mils in our EVMs.

    The uncoupled length should also be minimized as much as possible. The uncoupled near the processor is not too bad but the uncoupling near the USB connector can be improved.

    You can not lower the USB clock, it is embedded on the USB signal.

    Regards.

  • 0 in reply to Elias Villegas M.
    Expert 2750 points

    Elias,

    Thanks for the answer.

    Regarding the clock, although it is interleaved with other USB signal, ultimately it is still derived from the input clock and the USB module’s clock divider. Therefore as long as we are able to control the clock rate (by changing system/module clock multiplier and divider), I guess we would be able to control the USB clock rate, when it is acting as host?

    On the other hand when acting as peripheral, since the host (such as a PC) needs to query the device for device descriptors and else information including clock rate, why could we not using this chance to report a “lowered” clock rate to the PC, or simply reporting to the host in the “query reply” that is requires a low speed?

    Or, perhaps because USB speed is identified by the pulling up resistor of U- and U+ lines, so we CANNOT arbitrarily “falsify” an intermediate clock rate?

     

     

    But what clock rate is the “3mil” mismatch tolerance was the EVM designed for? Even if operating at full speed (12Mbit/s), it is actually still a very low speed signal in modern processors (and what if operating at 1.5M/bits low-speed?), and the 50mil mismatch is only 1.25mm. USB extension cable used for connecting PC and peripheral are usually 1 meter long (1000mm), and I bet it is actually common for these cable’s inner layers of coaxial D+ and D- lines to differ by one or two millimeters, especially when the cable is wound or twisted which experience shows that they doesn’t cause trouble (at least for most USB flash drives, microphones, webcams).

    So is the “3mil” or “5mil” tolerance designed for high-speed (480Mbit/s) communication?

     

    And in terms of the final “twisting” of D+ and D- lines shown above, is it NOT the most important problem as long as the TOTAL length of the two lines are properly matched?

     

    Paul

  • 0 in reply to Elias Villegas M.
    Expert 2750 points

    Elias,

    Could you give some furthe suggestions on the following-up questions just updated?

     

    Paul

  • 0 in reply to Paul Singh
    TI__Guru* 76130 points

    Hello Paul,

    As you said, the speed is dictated by the pull-up no DP or DM, you can not then modify the frequency of the USB signal, you should populate the pull-up on DM for the lowest data rate.

    The 3-5 mils is indeed for high-speed, working at low speed you should be fine with 50 mils.

    You are also correct on the severity of the "twisting" on the USB lines, you shall avoid this by changing the routing to the connector or changing the connector position.

    Regards.

  • 0 in reply to Elias Villegas M.
    Expert 2750 points

    Elias,

    We have modified accordingly. Thanks for the answer.

     

    Paul