• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 33 subscribers
  • Views 277 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS92LV2412 Lock drop due to power supply noise

John Merrill
Intellectual 420 points

I currently am using a DS2LV2412 on my display, and it often looses drop when certain patterns are displayed.  I believe it is due to my voltage regulators.  currently my set up is:

my power source is a 4.2V Li-ion battery

 

3.3V Buck regulator to pins VDDIO 1, 2 & 3

1.8V Buck regulator to pins VDDL, VDDSC 1 & 2, VDDR1 & 2, VDDIR, & VDCMLO

I am using a pi filter.  front capacitors are 10uF in parallel with 0.1uF to gnd through a ferrite bead, with a 0.1uF cap to ground following the bead in front of the power pins as shown in the datasheet.

I believe that I am still having noise issues with my regulators.  If I  increase the switch speed I get improved lock reliability, but not elimination of the problem.  I think that adding an LDO on the outputs of my buck regulators will solve the problem, could this be so?  I am interested in using the TPS73501 (adjustable version of TPS735xx family).  Will this be a good fit to eliminate the noise?

 

Thanks,

John

 

  • 0
    TI__Expert 3050 points

    Hi John,

     

    Power design issues could be an issue, but pattern dependant issues usually point to signal integrity problems on the parrallel bus for these parts.

    Can you probe the input signals on the serializer? Please check that the signals do not dip below ground or above VDDIO. If you find that your signals are violating the datasheet specs for VIH and VIL then you can consider adding termination resistors or adjusting the drive strength of the source.

    For power related issues, please probe the serializer and deserializer power rails under these good and bad patterns.If you notice that the bad patterns are causing the power supply noise to spike you could consider adding additional bypass caps to the impacted rails.

     

     

    Mike Wolfe

    DPS APPS / SVA

  • 0 in reply to Mike Wolfe
    Intellectual 420 points

    Thanks Mike,

    We had done just what you said.  The signals into the serializer are within the limits.  Power to the serializer also looked very clean.  Unfortunately I don't have the equipment required to monitor the serialized data so I wasn't able to verify those signals.  However, prior experience using a capable scope to validate the signals in my system has shown me that if the data into the serializer is good then the data out is also good on both sides of the coupling caps.

    When looking at the deserializer, I could not distinguish a difference on the power rails (which are different from the serializer) between a "normal" screen display and a display in which the deserializer lost lock.  I experimented with the voltage regulator by changing the switching frequency and increasing the decoupling capacitance  on the power rail locally at the deserializer. 

    Increasing the regulators switch frequency and the decoupling capacitance reduced the "loss of lock" events but did not eliminate them.  This lead me to the possibility that the regulator is either too noisy or can not adapt fast enough to the current requirements of the deserializer (when the regulator's switch frequency is 4Mhz). 

    So I added an LDO after the switch mode regulators (3.3V & 1.8V) to smooth out the power.  This completely eliminated the loss of lock.  We have evaluated this fix under all conditions for our device.  I added the LDO because of what I read in section 6.1 of the Channel Link II Design Guide.  This section discussed about the possibility of using switch mode supplies, but recommend the use of LDO's.  This information would be helpful in the datasheet for this part.