TL16CP754C Errata running with 1 stop bit

Hello Tom,

   Yes, the device is affected by the errata and the work around would be to change the baud rate configuration. Could you share information about your crystal and the desired baud rate?, also please provide a scope capture of one transmitted byte, in order to review the double start bit issue.

Best regards,

Diego.

Customer response is as follows, using their very accurate osc with a down stream system they still see the failure on a very rare occation.  They are concerened becuase with a very accurate osc they don't expect to see an error they would like to better understand the failure mechanism. 

We really need to know what is the tolerance on Baud rate and possibly stop bit time so the system can operate with the following setup.

1)      Baud rate 57,600

2)      Start bit = 1

3)      Stop  bit = 1

The specification we are operating under requires us to be able to communicate with other devices using the setup above with a 5% tolerance.

Given that we are using a very accurate oscillator of .01 %, it would seem that another  device we are communicating with should be able to vary very close to the +/- 5%.

After reading the errata and doing some calculations it seems the short stop bit time of -5.7 % is the problem.

Given that this is beyond the spec, do we have a problem?

1)      It appears our device sends a stop bit followed by a start bit, that appears to be 2 stop bits.

Hello Tom,

     What's the oscillator's frequency?, the -5.7% error  is calculated after or before implementing the workaround described by the errata?.

    The only way to solve this is by re-configuring the Divisor Latch Registers and maybe change the input clock frequency.

Best regards,

Diego.

Diego,

The customer's osc is as follows :

Our oscillator frequency is below at 7.xyz meghz
We divide by 8 and 16, we are using a 100 ppm oscillator

With this OSC the customer can create a very accurate 57600 baud output.   The issue is the other end of the line.  If that device is sending out a clock that is off how far off can that clock be off before this problem using only one stop bit.

Regards,

Tom

Here is some more detail on the way the part is configured:

" Our oscillator frequency is 7.3728 MHZ and our baud rate is 57600 bps. The internal UART divisor is 8 I believe.

Unfortunately this gives us no leeway to slightly adjust the baud rate.”

The divisor is 8.

Here is a snippet of the software code that sets this:

Here is the code snippet that calculates the divisor latch setting:

                // Compute Divisor Latch Setting based on configured Baud Rate

                divisor =

                    ((BSP_RS485_PORT_CLOCK_FREQ/BSP_RS485_PORT_PRE_SCALAR)/

                     (pCfg->BaudRate*16));

The BSP_RS485_PORT_CLOCK_FREQ equals: 7372800

The BSP_RS485_PORT_PRE_SCALAR equals:  1

7372800/ (57600 * 16)  =  8

Hello Tom,

    Is it possible to change the crystal?, if the customer increases the input frequency then they will have a wider flexibility to modify the configuration on the Divisor Latch Registers.

Regards,

Diego. 

They can't change the frequency.  The system is already in the field.  

Regards,

Tom

Hello Tom,

    The only possible solutions for your problem were already and covered and rejected by the customer, I am sorry but there is no more we can do to solve this issue. 

Regards,

Diego.