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Power down mode of DP83620

Hemant Ghayal
Intellectual 265 points
Other Parts Discussed in Thread: DP83620

Hello,

 

I have some queries about POWER DOWN Mode of DP83620 through assertion of pin 7.

1. How much time (maximum) is needed to enforce a power down during chip operation

2. When in power down mode, if the configuration is 100Base -FX, does the chip stop driving the Fiber Optic Transceiver so that the transceiver stops sending optical signals to the fiber  and goes silent.

3.Once Power Down is deactivated, how much time(maximum)  is needed for the chip to start functioning again?

4.Are all registers which were programmed before entering the Power down mode trough pin 7 preserved during the power down? A particular register of interest is the one used for Synchronous Ethernet Mode.

With regards,

Hemant

  • 0
    TI__Mastermind 31600 points

    Hemant,

    I will have to double check on the maximum timings for activation and deactivation of power down.  I can address your other two questions immediately.

    2.  When in power down, the DP83620 will stop the transmitter.  Therefore, the device will not send any signaling to the optical transceiver. 

    4.  The register configuration of the DP83620 is preserved during Power Down mode.  Registers programmed prior to assertion of Power Down will retain their programming.  This includes the configuration of Synchronous Ethernet mode.

    Patrick

  • 0 in reply to Patrick OFarrell
    Intellectual 265 points

    Patrick,

    Thank you. I do await the info on activation/deactivation delay w.r.to power down through pin 7.

    Also do let me know if the far end fault reporting feature of the 100Base-FX mode can be disabled as I envisage operating DP83620  in transmit-only or receive-only mode and I do not want this feature to interfere my operation.

    Hemant

  • 0 in reply to Hemant Ghayal
    TI__Mastermind 31600 points

    Hemant,

    Far End Fault Indication (FEFI) can be disabled via the FEFI Enable bit (bit 3 of register address 0x16).

    The Unidirectional Enable bit (bit 5 of register address 0x00) enables 100 Mb transmit activity independent of link status.

    Patrick

  • 0 in reply to Patrick OFarrell
    Intellectual 265 points

    Patrick,

    1. I  understand now that even though the bit FEFI_EN is set on power-on for Strap-selected Fiber operation, it can be reset, in which case the device will not send the FEFI pattern on receipt of fiber fault on its Rx. This feature, coupled with UNIDIRECTIONAL ENABLE BIT will allow complete separation of transmit from receive.

    2. So now  I need to know how fast I can cut off the optical transmission  or enable it. As I see the only way to control it for DP83620 is through pin 7 (PWDOWN)  of DP83620.  I await this information.

    3. I also understand that if I PWRDOWN the device through pin 7,  I cannot anymore use the device for receive, and hence may have to use a separate devices for receive if I want to continue receiving simultaneously. Do you agree to this?  Or is there a better and faster way of cutting off optical transmission (apart from pin 7 PWRDOWN control)  without affecting the device  RX?

    Hemant