Hello,
I have some queries about POWER DOWN Mode of DP83620 through assertion of pin 7.
1. How much time (maximum) is needed to enforce a power down during chip operation
2. When in power down mode, if the configuration is 100Base -FX, does the chip stop driving the Fiber Optic Transceiver so that the transceiver stops sending optical signals to the fiber and goes silent.
3.Once Power Down is deactivated, how much time(maximum) is needed for the chip to start functioning again?
4.Are all registers which were programmed before entering the Power down mode trough pin 7 preserved during the power down? A particular register of interest is the one used for Synchronous Ethernet Mode.
With regards,
Hemant