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SN65LVDS4 non 50% duty cycle operation

Victor Sinow
Prodigy 10 points

Other Parts Discussed in Thread: SN65LVDS4

Hello.

I am having difficulty with an AC coupled LVDS system composed of a SN65LVDS105PW driver and a SN65LVDS4 receiver.

The circuit is constructed as recommended in the "AC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML" guide, http://www.ti.com/lit/an/scaa059c/scaa059c.pdf page 7 figure 11.

The issue arrises when I attempt to send a square wave through the system with non-50% duty cycle (10MHZ < Fs < 100MHZ). Specifically, the pulse width skew is significantly higher than specified in either part's respective datasheet. At 50%, the low going prop delay and the high going prop delay (measured from single ended input of 105PW to single ended output of LVDS4) are very well matched, however, at duty cycles other than 50%, there is significant prop delay mismatch, which manifests as pulse width fidelity problems from input to output. An additional oddity is that at high duty cycles, the low going prop delay is much shorter that the high going prop delay (> 2ns difference), whereas at low duty cycles, the behavior reverses and the high going delay is shorter than the low going delay.

Can anyone tell me what is going on? Is this expected behavior? Can I restructure the circuit to enable Tplh=Tphl at any duty cycle?

Thank you in advance!

  • 0
    TI__Intellectual 2460 points

    I just now simulated your situation. and let's see the theory. the circle may not be accurately the same with yours. but it doesn't matter for the theory.

    1 We know the capacitor blocking the DC. so what will non-50%duty cycle signal become after the capacitor? In the picture we can see that. Because there's no dc components, the signal changes. the pulse is high and the mid-point is not GND( if 50%duty cycle, the mid-point is still GND).

    2 We should know there's a period from low to high. So when the input signal pass the threshold, the output signal changes. the threhold is commonly 0 or voltage about 0(e.g. ±50mV). So there needs more time that the input ac-coupled signal changes from high to 0 and less time from 0 to low. The ratio changes, not 1:1. So it will change the output duty cycle. If it is a ideal sharp edge, there will be no this problem.

    Above all, i think it is the' ac-coupled' that affects the output duty cycle deviation, rather than the LVDS4. I don't know what I said is clear to know. Welcome comments.