PCI 2050B Configuration with MPC8548E Processor

Hello,

There is not timing requirement between P_VCC and S_VCC, but please note that both S_VCCP and P_VCCP should be powered prior to VCC being applied.

Can you share your schematics?

Regards.

Hello Villegas,

Thanks for your reply. But i am confused with respect to  "P_VCCP and S_VCCP be powered prior to VCC being applied". Please refer following link posted by DK.

http://e2e.ti.com/support/interface/digital_interface/f/130/p/71449/261173.aspx#261173

"As for power sequencing, assuming this is a 3.3V only solution, there should be no issue powering both VCC and VCCP from the same rail".

I have attached the schematic.

Regards,

Ravi Shankar

Schematic PCI 2050B

Motherboard side

Pull up

Hello Ravi,

We are going to review the schematics, regarding your question about voltage rails:

The VCCP pin the input for a protection diode array that protects the PCI I/O pins from an overvoltage condition. If VCC is applied before VCCP, then the protection diode could turn on and remain on until VCCP was brought up. Since this could be a reliability concern for 5V systems over a very long period of time, we advise customers to power VCCP prior to VCC just to be safe.

In cases where powering VCCP prior to VCC is not practical , we recommend a 1K resistor in series to the relevant clamp rail of each pin (S_VCCP and P_VCCP).

Hi,

Waiting for your reply.

Pleas Respond.

Do you have reference device drivers available for PCI 2050B?

Thanks in Advance..

Hello,

the logic capture you attached looks incorrect.

The FRAME# signal is not being asserted in the correct way, neither the DEVSEL, was this capture taken from the primary or secondary side?

I reviewed the schematic and have some comments:

Place a 10K pull-up on S_RST#.
Place a pull-down on JTAG_TRST#.
Resistors R275, R276 and R449 shoud be 1K.
Interupt lines are routed around the PCI2050B, but that interrupt mapping should match the AD lines used as IDSEL, according with Table 3-2 of the datasheet and the picture attached here below.
Make sure you have all the required pull-ups per PCI spec.

Hi,

Thanks for your reply. The Captured signals are from secondary side of the bridge. My configuration cycle of the device is ok as i am able to read the vendor ID and Device ID. But, I have incorporated the suggested hardware and software changes, still i am facing the similar problem. My read and write cycle is not happening.

Regards

I have also verified the schematic for the PULL up as per PCI Specification. Is the Buffer will matter? I am connecting a level converted as V6(FPGA) operates in 2.5 V and PCI operate in 3.5 V.

Hello,

Yes, the voltage level translator will matter, what device are you using for that? Can you send a logic capture of one write/read transaction?

Regards.