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Broken capture with Aptina AR0331 and SN65LVDS324

Lajos Rancz
Expert 1065 points
Other Parts Discussed in Thread: DM385

Hi all,

We use the Aptina's AR0331 3MP WDR image sensor with TI's SN65LVDS324 LVDS parallel converter in our DM814x based IP camera. It seems that if we pause the sensor streaming (which is frame synced and does not produce bad frame) the LVDS324 will go crazy and eliminate frame sync signals. This results broken pictures (see below). What's wrong? How could we fix it?

Regards,
Lajos 

  • 0
    TI__Guru* 76130 points

    Hello,

    Can you send the values you are writing to the CSRs on the LVDS324?

    What is the pixel clock and resolution?

    Regards.

  • 0 in reply to Elias Villegas M.
    Expert 1065 points

    Hi Elias,

    Here is a snippet of our init method:

    SetReceiverReg(0x09, 0x2C);
    SetReceiverReg(0x0A, 0x32);
    SetReceiverReg(0x0B, (unsigned char)((mSensorSize.width >> 8) & 0xFF));
    SetReceiverReg(0x0C, (unsigned char)(mSensorSize.width & 0xFF));
    SetReceiverReg(0x0D, (unsigned char)((mSensorSize.height >> 8) & 0xFF));
    SetReceiverReg(0x0E, (unsigned char)(mSensorSize.height & 0xFF));
    SetReceiverReg(0x0F, 0x00);

    The resolution is varied (648x496, 1288x978, 1928x1458, 2048x1536 (standard resolutions + crop for pipeline). The pixel clock is 100 MHz, 1 ch, 4 lane, 12bpp. Interesting to note that incidence of brokening is higher if we choose the CLKOT = 64.7 to 120 Mhz against the CLKOUT = 118.7 to 162 MHz.

    Regards,
    Lajos 

     

  • 0 in reply to Lajos Rancz
    TI__Guru* 76130 points

    Hello Lajos,

    Writing 0x2C to offset 0x9 configures the LVDS324 as 1-channel 4-lane 12bpp and clock centering for OMAP processors.

    I recommend to set bit-3 of the offset 0x09 to 0 in order to configure it for Davinci processors.

    The 1-channel 4-lane 12bpp requires a system clock of 222.75MHz, and the output clock will be 148.5MHz, can you configure your sensor to output the required frequency?

    I'm afraid the 100MHz clock is causing the loss of sync.

    Pleas try also to reducing the slew rate (bits 5:4 offset 0x0A)

    Do you see the issue setting the LVDS324 in TEST MODE?

    Regards.

  • 0
    Intellectual 270 points
    Hi Lajos,

    It will be great if you can help me out !

    I am trying to configure the AR0331 using LVDS324 on DM385 based IPNC, I have configured the 0x09 and 0x0A register on LVDS324, but I am not getting frame on application. So you can please tell me how to get the frame in application, It will be great If you can tell me what settings you do in order to get the frame in application.

    Please let me know