TLK2226 connected to a FPGA(MAC) in our project which was developed in 2010 and has been in mass production. But recently in one of our customer's testing they found just 6-byte preamble + 1-byte SFD are received on the line (they got an equipment to monitor the PCS layer).
After confirming the FPGA codes and simulation, the total 7-byte preamble+1-byte SFD are sent out by MAC of FPGA.
I am wondering whether TLK2226 PHY could be capable of shrinking the preamble bytes from 7 to 6? or even smaller?
