TUSB1310A PHY status

Chris Zhao1

Expert 1240 points

Other Parts Discussed in Thread: TUSB1310A

Hi, experts

I designed a board based on TUSB1310A, while I can't generate PCLK.

I'm sure power rails are ready, there is nothing wrong with 40MHz clock input, and OUT_ENABLE is pulled up.

a) I'm confused about "Internal resetn/PLL_EN/SUSPENDM", is it a signal I should control, is it PHY_RESETN?

b) About PHY_STATUS/ULPI_DIR, should I control this pin, what do you mean by it in this diagram? I found PHY_STATUS/PIPE_16BIT was input/output pin, under which condition, it is input, or output?

c) The strap pins which are latched in my design are

XTAL_DIS/RX_ELECIDLE (1, clock input),

SSC_DIS/TX_MARGIN0 (1, SSC disabled),

PIPE_16BIT/PHY_STATUS (don't know how to deal with),

ISO_START/ULPI_DATA7 (0, not isolate),

ULPI_8BIT/ULPI_DATA6 (0),

REFCLKSEL1/ULPI_DATA5 (1),

REFCLKSEL0/ULPI_DATA4 (1)

Is there anything I missed?

Thanks.

Chris.

over 11 years ago

0 Diego Cortes over 11 years ago

TI__Mastermind 36085 points

Hello Chris,

We are reviewing your post and we will reply soon.

Regards,

Diego.

0 Chris Zhao1 over 11 years ago in reply to Diego Cortes

Expert 1240 points

Hi, Diego

No problem.

Thanks.

0 Chris Zhao1 over 11 years ago in reply to Chris Zhao1

Expert 1240 points

Hi Diego,

This problem has be solved. It was caused by JTAG signals. In my schematic there is FPGA, PROM and TUSB1310A in JTAG chain, At first I bypassed TDI and TDO, but there is still TCK inputs for TUSB1310A. So some action was caused by TCK. By this I mean during normal operation, if there is valid TCK inputs, TUSB1310A can't run correctly.

I still have another question about STRAP pins, e.g. XTAL_DIS(RX_ELECIDLE) S, I/O, PD, in which condition it is input, or output. I didn't find it in datasheet.

Thanks.

Chris.

0 Chris Zhao1 over 11 years ago in reply to Chris Zhao1

Expert 1240 points

Hi Diego,

After I isolated TCK, I can monitor PHY PCLK. While there is something strange. I design a counter inside my FPGA, when then counter reaches 100, it inverts the output signals, so the output should be 2.5MHz, while I get a image like below.

It seems sometimes there is no clock output from PHY. Every 208us it will repeat, and the duration is 52us.

Could you tell me why?

Thanks.

Chris.

0 Chris Zhao1 over 11 years ago in reply to Chris Zhao1

Expert 1240 points

Finally, this problem has been solved. TUSB1310A hasn't been configured properly.

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TUSB1310A PHY status