Hi Team,
Our customer is now evaluating TSB81BA3E and receive the output by FPGA. They need to verify the timing requirement between TSB81BA3E and FPGA. But the delay time, td is only defined typ value and do not have maximum value, so it can not be guarantee the timing requirement at FPGA side.
Please let us know how should the user verify the timing requirement?
Best Regards,
Sonoki / Japan Disty
