UVLO operation of SN65HVDA1040A-Q1

Hi Masami,

- When the UVLO of Vcc operates, does RXD pin stop operation? Does a logical output serve as 'High' then?

• I will check with our design team about the state of RXD. I would imagine that the pin would just be in a high impedance state (from looking at the equivalent circuit schematics on page 15 of the datasheet. If you want to guarantee a state, you can use an external pull-up resistor.

- Does hysteresis stick between rise edge and fall edge of a power supply about threshold of UVLO of Vcc?
When attaching, how Volt is it generally in a typical value?

• I will also have to check with the design team about hysteresis, and if there is built in hysteresis what it's value is.

- About TXD Dominant State Timeout. I want you to teach the release method after TimeOut occurs.

• The dominant state timeout is activated when the TXD pin is held low for longer than TDST. The device automatically resets the timer when a rising edge (recessive edge) on TXD occurs. For example, if TXD is held low for 1ms, the timer trip and the driver will release the bus at the latest of 700µs. The device will be in the time-out mode (TXD is still low, but the bus is recessive) from 700µs till 1ms, and then when the TXD pin is release at 1ms, the device will be back into normal operation.

Thanks,

John

Hi, John

Thank you for your reply.
I answer it to a customer.

Thanks, Masami M.