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Issues with SN65LVDS324ZQL

Elad Segalis1
Intellectual 760 points


 Hi,

We are using AR0330 sensor from Aptina in HiSPI mode.

The sensor configure to output 2304x1296 pixels at 30fps.

The sensor connect with SN65LVDS324ZQL to convert the HiSPI data to parallel.

The serial input clock to the SN65LVDS324ZQL is 150MHz

Most of my boards are working fine, however in some boards we get very strange instability of the video stream.

 we get the end of one frame (VSYNC) too soon, and the new frame starts. (the result is two cut frames together with a black  rectangle in the middle)

We are having a hard time to find out the root cause of this issue, but it seems that the HiSPI interface that the SN65LVDS324ZQL recives works perty well.

In addition to the questions above I cannot find in the datasheets the description of bits 3:2 in register 0x0A, so I am not sure how I should set these bits.

Please advise

Thanks

 

 

 

  • 0
    TI__Mastermind 36085 points

    Hello Elad,

        Regarding the issue we are reviewing your post and we will reply soon. I am looking on the information about the register 0x0A, however I think that the missing bits is because these bits are reserved.

    Regards,

    Diego.

  • 0
    TI__Guru* 76130 points

    Hello Elad,

    Can the customer easily reproduce the issue? 

    What are the values they are writing to addresses 0x09 to 0x22?

    Can they be sure that the sensor is not generating a wrong End-of-frame?

    Are they able to reproduce the issue if they set the LVDS324 in TEST MODE?

    Is the bit SOF_ERR set when the issue occurs? (address 0x11)

    All the Registers in the LVDS324 must be set before SCLK is applied.

    Regards.