Clock Buffer with failsafe

Toshiyuki

Mastermind 7075 points

Other Parts Discussed in Thread: DS90LV110AT, CDCLVP110, CDCLVP111

Hi,

Customer requests　clock buffer under the following conditions.

①VCC Supply :3.3V

②1:10 output clock buffer - LVPECL with failsafe

③Input clock source is 1.8V/HSTL/164.426MHz or 3.3V/LVPECL/164.426MHz or 1.8V/HSTL/169.409MHz.

DS90LV110AT is supporting LVDS.

Do you have a proposal?

Best Regards,

Kato

over 11 years ago

0 Michael Peffers over 11 years ago

TI__Mastermind 20820 points

Hi Kato,

Is the fail safe a necessitate?

We have the CDCLVP111 and CDCLVP110 which will support your requirements except for the fail safe.

Is 3.3V a hard requirement as well or can you work with a 2.5V rail? We may have some other parts I can look at for 2.5V if this is acceptable.

Regards,

Michael Peffers

Analog Applications Engineer

0 Toshiyuki over 11 years ago in reply to Michael Peffers

Mastermind 7075 points

Hi Michael,

Thank you for the answer.

Our customer requires the fail safe.

If they can work with a 2.5V rail, let me know some other parts.

Best Regards,

Kato

0 Michael Peffers over 11 years ago in reply to Toshiyuki

TI__Mastermind 20820 points

Hi Kato,

I do not support the clocks and timing products but from a quick seach on TI.com it looks like the DS90LV110AT will support the customers requirements.

http://www.ti.com/lit/ds/snosac2j/snosac2j.pdf

In the part description it says that the input supports LVDS, LVPECL, and PECL inputs. If you refer to the Clocks and Timing Forum for your follow up questions regarding this topic you will most likely get better answers since they support these products.

Regards,

Michael Peffers

Analog Application Engineer

Interface

Interface forum

Clock Buffer with failsafe