Bus fault in redundant configuration

Hi Livio,

Since there are two completely separate physical layers, they should operate independently from each other. Therefore, an error on one should only momentarily cause an error on the other.

Even if one bus got stuck in a dominant state the bus would only block communication on the combined RXD pin for RXD dominant timeout, before the transceiver with the fault would release the RXD pin to a high state (idle). It looks like you are handling the faults individually instead of combining them with an XOR gate. Would you be able to share a couple screenshots of different combinations of signals when the issue is occurring (you most likely will not be able to show both TXD signals, both RXD signals, the Fault lines and the bus signals on one scope, unless you happen to have a mixed signal scope available).

Thanks,

John

Dear John,

Thanks for your response.

As you can see from the attached screenshots, the problem appear only with a single cut failure near the module. In this case (screenshot-1), strangely the RX-B signal which is interrupted is present at RX pin of the driver, but the transmission in this condition fails.

Screenshot-1

If I force the driver B in silent mode (screenshot-2) all is OK. The driver B RX signal is still present but it cannot transmit any bit because it is in silent mode.

Screenshot-2

Also if I do a single cut, away from the module all is OK (screenshot-3) because in this case the RX signal on driver B is  correctly not present.

Screenshot-3

Here you can see the schematic of my circuit.

8103.CAN SCHEMATIC.pdf

Regards

Livio    

Hi Livio,

Thanks for sharing the schematic and all the screenshots! This is very helpful.

One guess that I have is that the local node, with the cut wire, is missing the ACK delimiter bit. When it expects to see a recessive level, and instead sees a dominant level, it will send an error to the bus blocking communication.

If you are not familiar with the standard Data Frame in CAN, it is made up of several fields, the last three being a CRC field for error checking, an acknowledgment field so the sending node can verify if the other nodes on the network received a valid message, and the end of field frame used for signaling if a frame needs to be resent, or if a node is overloaded.

The acknowledgment field, is where I think the issue is occurring. In this field the sending node sends a recessive bit to the bus, and listens for a dominant bit to be sent to the bus from all the receiving nodes. This bit is followed directly by a recessive delimiter bit. It is the job of every listening node on the network to run a CRC check and compare it to the CRC check that is sent by the sending node. If they match, the receiving node sends a dominant bit, if they do not, then the receiving nodes send a recessive bit. Under normal circumstances many nodes will be sending a dominant bit at the exact same time verifying a valid message was sent.

In networks with lots of nodes all driving the bus in parallel a much more dominant signal will be seen on the bus and all the capacitances on the bus will be charged to a higher level. This results in a longer decay time for the bus to get back to the recessive level. Since only a single bit time is allotted for this to happen, it is very common for this bit to be the cause of errors on a CAN bus.

To further explain what I think is happening with some math, a normal bus with proper termination the differential resistance is ~60Ω, which is the driving force bringing the bus back to a recessive state.  If the network has between 10 and 100 nodes, and we estimate that each node contributes 100pF of single ended capacitance to the network, then there will be a total of 1nF to 10nF of capacitance on CANH and CANL. This results in a time constant that ranges from 60ns to 600ns (60Ω* 1nF or 10nF).

Now if we disconnect on of the CAN bus wires from the network, it will no longer have the termination resistance driving it back to the 2.5 volts recessive state. This could result in it taking more time for the voltage on this bus pin to decay. If we take the 100pF of single ended capacitance again, with only the internal 15kΩ resistance driving it back to recessive state, this results in a time constant of 1.5µs. This results in it taking 2.5 to 25 times longer for the bus voltage to decay.

I think if you take a screenshot of CANH and CANL on the transceiver that has the cut wire, we may be able to see if this is the cause of the issue. Hope this helps, please let me know if you have any questions.

Thanks,

John

Hi John,

Hi John,

Thanks for your response.

Now all is clear.

Regards

Livio