Hi,
The APP note for the 1394 PHY TSB81BA3E makes a somewhat vague reference to a timing relationship between TPA and TPB as it relates to matching etch lengths for the path from the connector to their respective pin pairs. I was looking for some more detail on how matched they have to be before there is a performance hit. Our current production board has a 50 ps etch delay mismatch between TPA and TPB diff pairs and am wondering if this may be contributing to what appears to be marginal performance with long cables operating at S800 when compared to same link terminated into a PC based system.
Thanks,
Mitch