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TUSB1310A PHY_STATUS no operate

SeokYeon Jeong1
Prodigy 30 points
Other Parts Discussed in Thread: TUSB1310A

I am trying to operate with TUSB1310A for USB SuperSpeed device.

But the initial operation is not good.

Please see the below figures.

In the above figure,

1. "usb_rst_n (RESETN)" and "phy_rst_n (PHY_RESETN)" is asserted (to low)

2. after about 440ns from reset de-asserted, "phy_status(PHY_STATUS)" is asserted during ~50us.

    at the same time, "rx_elecidle" is asserted.

    at this time, the "power_down" is 'd2.

    and PCLK is always running at 250Mhz.

3. after about 300us, the "power_down" is changed to 'd0.

4. after about 1.7ms, the "rx_termination" goes to high.

   and then "rx_elecidle" is toggle with 1us low and 9us high

I think the "phy_status" should be asserted one clock when "power_down" is 'd0.

but there is no "phy_status" toggle, so link logic is time-outed.

the above figure is long time (400ms) capture.

1. "power_down" is 'd0, and after the "rx_termination" goes high, there are many "rx_elecidle" toggle.

     but there is no "phy_status", so link logic is time-out and then "power_down" goes to 'd3.

     in this state, the "PCLK" is still running with 250Mhz frequency.

     (the PCLK  should be off when P3 state???)

2. after 100ms P3 state, "power_down" is 'd0, but still no activity in "phy_status".

3. "power_down" changes to 'd2, and after 100ms the "tx_detrx_lpbk" goes to high, but still no activity

    at the TUSB1310A outputs.

I checked the initial strap option pins state.

Could you check this problem ?

One more question.

If the "JTAG_TRSTN" is floating, is there any problem for normal operation ?

Thanks in advance.

  • 0
    TI__Mastermind 36085 points

    Hello,

    Regarding to your questions

    The PCLK  should be off when P3 state? yes it should be off and  the PIPE is in an asynchronous mode, PLL is off and PHY_STATUS is asserted before PCLK is turned off and deasserted when PCLK is fully off.

    If the "JTAG_TRSTN" is floating, is there any problem for normal operation ? This is a possible source of the issue, please add a PD resistor to this terminal.

    If the previous suggestion does not work, I think we have to start the debugging from the beginning, Could you confirm the following power-up sequence?

    Best regards,

    Diego. 

  • 0 in reply to Diego Cortes
    Prodigy 30 points

    Thanks for you reply.

    As you suggest I add a PD resistor to the "JTAG_TRSTN", but there is no effect and no difference with previous.

    I checked the above power-up sequence, and the result is as following figure.

    1.  "usb_rst_n (RESETN)" and "phy_rst_n (PHY_RESETN)" is asserted (to low) during 60us.

    2. The strap option pin (tx_margin[0], ULPI_D[7:4], PHY_STATUS, RX_ELECIDLE) is valid

         when "RESETN" de-assert.

    3. "PHY_STATUS" is asserted during 50us.

        (the difference with your power-up sequence :

          1) the PHY_STATUS is not high when RESETN is low because this pin is strap option pin for "PIPE_16BIT")

          2) the PHY_STATUS is asserted only 50us not 300us. (Is this problem?)

    3. "ULPI_DIR" is high during 300us after RESETN de-assert.

    3.. PCLK is low when RESETN assert, and after 7us, the clock is out. (the logic analyzer sampling is 2ns).

    the following figure is 250ns sampling result.

    I think there is no difference with your power-up sequence except for "PHY_STATUS".

    When I set the USB link logic to "high-speed" or "full-speed", the ULPI interface of TUSB1310A works well.

    Only the PIPE interface does not work.

    Could you tell me more suggestion to solve this problem?

    one more question.

    Could you tell me the meaning of the strap option for SSC_DIS (TX_margin[0]) ?

    I set this pin to high or low, but there is no difference.

    Best Regards,