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DP83848K start-up

Other Parts Discussed in Thread: DP83848K

We decided to use DP83848K as a PHYter for the 9th MAC port of Realtek switch controller RTL8309. Apparently, DP83848K has a very slow start-up, it takes up to ridiculously long 140ms delay until DP83848K starts to generate TX_CLK and RX_CLK (25MHz for forced 100Mbit mode). By that time ethernet switch controller already decides that there is no external PHYter and disables this MAC port. Though, if I reset both chips with a reset button (while power is already present), DP83848K starts to generate TX_CLK and RX_CLK instantly. That is, if I press a reset button (after powering up the PCB) our switch starts to work as expected - 9-port Ethernet Switch. But it never starts to work properly during normal power up.

My impression, internal Brown-Out-Detect circuit is unnecessary slow (140ms delay in the modern world is a humongous time interval).

Workaround is: put a 200-250ms delay on a switch controller reset input. And now our switch starts to work properly during normal power up.

The questions:

1) why DP83848K has so loooong start-up (BOD?)? Is there a way to shorten it?

2) documentation on a DP83848K says nothing about specs on this start-up time. What is a worst case scenario? I have to take the slowest start-up time into account (to develop a schematic which will work all the time)?

  • What is the starting point for your measurement of start-up time?  Are you measuring from the beginning of the power supply ramp or the beginning of a reset signal or something else?

    What is the source of the DP83848K input reference clock on the XI pin?  Is this a crystal or an oscillator or is it sourced from another component on the board?

    Since you refer to the start of TX_CLK and TX_CLK, I would infer that you are operating in MII mode.  Could you please confirm?

    Patrick

  • sorry for insufficient details in my original post.

    Yes, I use DP83848K in  MII_mode.

    I have external reset generator (output is active low, until VDD reaches 2.93V). I use this output as a scope trigger.

    25MHz crystal is used (not oscillator). Though, I can see that crystal starts to oscillate even before RESET signal goes high (i can see oscillation when VDD is already slightly above 2V; for reference, during power up full rise time of VDD from 0 to 3.3V is about 10ms).

    Thanks,

    Andrey

  • Andrey,

    I believe this is related to crystal start up.  The datasheet parameters of interest would be in section 8.2.1 detailing power up timing. 

    The internal clocking of the device is based on this crystal input.  Since this is key to the functionality of the device and stable crystal oscillation can take time, the stabilization time was chosen conservatively. 

    Having noted that, what additional information can I provide to help optimize your system?  Aside from a hard reset, are there other alternatives for re-enabling the MAC port in the switch?

    Patrick