Hello,
we have a FPGA-based board with which we are driving the SN75DP130 device with HDMI 1080p @ 50Hz (through a Serdes Transceiver)
The Sink is then a HDMI screen, we connect from the SN75DP130 DP output to the HDMI screen through a DP2HDMI2 DP-to-HDMI converter from Startech ( http://www.startech.com/AV/Displayport-Converters/DisplayPort-to-HDMI-Cable-Adapter-Converter~DP2HDMI2 )
If we understand well, we should use the re-driver in TMDS mode, to be able to transfer HDMI signalling through the SN75DP130 re-driver. The FPGA Is outputting the HDMI signals correctly through the Transceiver 4 lanes :
3 lanes for RGB Video data and 1 lane for TMDS clock (pixel clock @ 148.5MHz). but nothing is displayed on the HDMI screen.
The same FPGA design is used on another board with direct connection from the FPGA serdes lanes to a HDMI connector, and it works fine (image displayed in 1080p - 50Hz)
We then have doubts on whether the SN75DP130 re-driver is in the correct TMDS mode and/or configured correctly.
Here is what happens : when we connect the HDMI screen, we see the CAD output from the SN75DP130 being '1', meaning we are in TMDS mode, as expected. Then, apparently, we alternatively go from Standby Mode to Active Mode, then Standby mode, Active mode again, etc ... (we monitored the HPD_SNK signal with a scope, and we see 1 -> 0 -> 1 -> 0 etc ... transitions ) showing that the link seems "not stable".
By the way, is there a way of knowing, through I2C readings, what is the Operating current mode ?
(as shown page 21/41, figure 25 of the SN75DP130 datasheet)
So, we are not sure of the SN75DP130 configuration :
- for TMDS (HDMI) video, should it work with the default configuration ?
or do we need to touch something on the I2C interface registers ?
- if we need to configure something, how ?
Can you help us with this critical problem ?
Thanks a lot for your support
(and I hope I am requesting the correct technical support, if not, can you advise me whom I should talk to ?)
Note : there is an error in the SN75DP130 datasheet for I2C reading procedure described page 27/41 : the read does NOT not occur at Register Offset 00h if you performed a write before !
To do a read, the user must write I2C first @ 0x00 to reset the internal address to 00h, then it can read starting from here. The datasheet is absolutely not clear about this, and should be updated.
