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XIO3130 access issue

alpha
Expert 2530 points
Other Parts Discussed in Thread: XIO3130

Dear Expert

There are some issue in our customer.
Could you please advice for issue ?

condition
CPU : Intel BayTrail-IE3845 1.91GHz Quad Core
OS : Windows Embedded 64bit
XIO3130 is connected to the ch3 of PCIE
ch1 and ch2 of XIO3130 is connected to the Spartan6 of Xillinx.
ch3 is opened because of unused.

They have tested and approved for use SandyBridge as extention board of FPGA.
They use the tool that is "Read&Write Utility" to test connection PCI devices.

There are 2 kinds of issue.

Issue 1
The device connected to ch1 cannot be accessed.
Clk is output during 2～2.4msec after startup , and then clk is stopped.
When ch1 is removed connection, clk is output 1msec ,and then clk is stopped immediately.


Issue 2
FPGA device connected ch2 has 3 area of memory and FPGA use BAR1,BAR3 and BAR4.
Although FPGA can access to BAR1 and BAR3 , FPGA can not access but can read only "0".

Best Regards

  • 0
    TI__Mastermind 36085 points

    Hello Alpha,

        Could you confirm the following information

        Please provide a block diagram of the system.

        Regarding to the passing test you mentioned, Did you use the XIO3130?.(SandyBridge + XIO3130 + Spartan6).

        Is the issue happening only on this OS (Windows Embedded 64bit)?

    Best regards,

    Diego.

  • 0 in reply to Diego Cortes
    Expert 2530 points

    Hello Diego.
    Thank you for your response.

    I got block diagram from customer.
    please see the attached file.

    This issue is confirmed only Windows7 Embedded 64bit but others is not tested.

    Best regards.

    6505.XIO3130 ACCESS ISSUE.pdf

  • 0 in reply to alpha
    TI__Guru* 76130 points

    Hello Alpha,

    Please provide the schematic, is the XIO3130 recognized by the Host?

    Are the FPGAs recognized by the Host if you remove the XIO3130?

    Regards.

  • 0 in reply to Elias Villegas M.
    Expert 2530 points

    Hello Elias

    > Please provide the schematic, is the XIO3130 recognized by the Host?

    I got schematic from customer but I hesitate to distribute customer's schematic on this web.
    Could you tell me your e-mail?
    I'd like to send schematic by e-mail.

    > Are the FPGAs recognized by the Host if you remove the XIO3130?

    Yes.Customer confirmed that FPGAs are recognized by the Host when XIO3130 is removed.

    Best  regards.

     

     

  • 0 in reply to alpha
    TI__Guru* 76130 points

    Hello Alpha,

    I reviewed the schematic and have some comments:

    1) You are not connecting DN2_PERST#, this signals must be connected to the downstream device.

    2) Please see the Errata #2 available at ti.com, it is possible the root cause, implement the workaround by connecting DNx_DPSTRP# terminals to 3.3V.

    3) Can you send scope captures of the power-up sequence showing UP_PERST#, UP_REFCLK,  VDD33, GRST#, and another one showing DNx_PERST#, DNx_REFCLK. 

    Regards.