USB 3.0 / 2.0 crosspoint switch

Hello Jonathan,

     What about to use a USB3 switch and a USB3 HUB. The HUB will provide connectivity on SS and HS to both USB ports at the same time (up to 4 downstream ports), meanwhile you can select the CPU by means of the switch.

The recommended parts for the implementation are:

    HD3SS6126 & TUSB8040A1.

Best regards,

Diego.

Hi Diego,

I attached below a block diagram with your suggested configuration.

Is the connection between the TUSB8040A1 and the HD3SS6126 going to be a significant bottleneck (since only one CPU can effectively use the USB hub at a time), or is there enough overhead in the USB standard that this wouldn't be a major concern?

This may be some ignorance of the protocol on my part, but if the keyboard is going to CPU A and the mouse to CPU B, and the HD3SS6126 is switching back and forth between the CPUs, is there an issue of losing packets as the HD3 is switching, or is this accounted for at some point and the suggested configuration is 'tried and true'?

Thanks for your insight on this.

Jonathan Bender

Hello Jonathan,

    Per USB specification, the bus has a tree topology with only one USB HOST. And on your system, each CPU is acting as a HOST, therefore you cannot have both CPUs connected to the same USB tree at the same time.

    Now, regarding to the behavior of my proposal: The HD3SS6126 will connect the TUSB8040A1 only to one of the CPUs, after the connection is between the HOST and the HUB is established, the HOST shall enumerate the HUB and all the connected devices to its downstream ports. On this way, the HOST will get complete access to the USB tree and all its devices. Each time you change the connection by means of the HD3SS6126, the selected HOST will initiate the USB enumeration process, meanwhile the other processor will lose the USB connection.

Best regards,

Diego.

Hi Diego,

So in the use case of the downstream devices being used by one CPU at a time, the above diagram would be a good solution.

But if we basically wanted to have one 'realtime' downstream device on CPU A and the other 'realtime' downstream device on CPU B, this would be problematic as the CPU would have to re-enumerate each time the HD3 switched.

So for the second case, with a 'realtime' downstream USB device assigned to each CPU, we don't have a single or maybe two-socket TI solution (like the 'Crosspoint Switch' block in the first diagram)? Would the four HD3 block diagram be about as close as we could get?

Thanks,

Jonathan Bender

Hi Jonathan,

    We have the TUSB8020B, which is a 2-ports USB3 HUB, but this part is under release process and is supposed to be available within this year.

Regards,

Diego.

Hi Diego,

This new part is just a hub and thus has a single upstream port, not two ports like I would need in this application to go to two different CPUs 'realtime', correct?

Thanks,

Jonathan Bender

Hi Jonathan,

    It is correct, It has only one upstream port and as I said before, per USB specification you cannot have such dual & real-time upstream connection. Now I am wondering Why you need such topology?, please share more information regarding the application, so I can help you to find the better possible implementation.

Best regards,

Diego.

Hi Diego,

I don't have any other application information currently other than what I've provided.

In the below block diagram, if I had the HD3s switched internally as the lines show, would that work?

If I wanted to put the mouse on the other CPU, for instance, I would switch the bottom-right HD3. There would only be a single host CPU per downstream device connected at a time. This is the closest approximation to a USB 3.0 / 2.0 crosspoint MUX I have been able to create.

Thanks,

Jonathan Bender

Hello Jonathan,

    The implementation is possible with the following restrictions:

    Each time you select a complete path between one processor and one device, the Host (CPU) will enumerate the attached device and this last one won't be accessible until the enumeration process is completed.

   Depending on the configuration of the HD3SS6126, The processors will be able to operate the devices as follows:

• CPU_A connected to DEVICE_A and CPU_B connected to DEVCE_B.
• CPU_A connected to DEVICE_B and CPU_B connected to DEVCE_A.
• CPU_A connected to DEVICE_A only.
• CPU_A connected to DEVICE_B only.
• CPU_B connected to DEVICE_A only.
• CPU_B connected to DEVICE_B only.
• NO accessible devices.

Is this what the customer wants?

Best regards,

Diego.

Hello Jonathan,

    It is impossible to have more than one device connected to the same Host port, the only way to have more attached devices is by means of a HUB (the first approach that I suggested).

Best regards,

Diego.

Hi Diego,

Understood, and the TUSB8020B in the above diagram is a hub, with the single upstream connection to the host (CPU A or B). The HD3 switches just switch DEVICE_A and DEVICE_B between HUB_A and HUB_B, so this configuration should be okay, correct?

Thanks,

Jonathan Bender

Hi Diego,

Thanks for all your help. I expect to have more application information in the coming weeks, and will contact you directly for further design-specific suggestions.

Thanks,

Jonathan Bender