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DP83848: request clarification of power up and reset timing

Tom McTaggart
Intellectual 345 points

I'm confused by exactly what the data sheet figure on Power Up Timing is saying.

1. the 167 mS min time to latch input pin states: what is the maximum? I'm assuimg the device cannot proceed unitl this occurs, so how long counld it be?

2. How does this relate to stable clock?

3. Where exactly does T2.1.2 start? At rise of RESET_N? Or what?

4. A typical oscillator starts up within 10 mS. Is it correct to say that we shoudl not release the RESET_N until the oscillator has stabilized? 

  • 0
    TI__Mastermind 31600 points

    The 167ms time for post power up stabilization is intended to allow for stable oscillation of an external crystal.  The internal circuitry needs to see a sufficient number of clock edges to confirm that the external crystal is stable.  The 167ms time was chosen to be conservative.  A crystal with a very slow oscillation could exceed this time, but this would not be typical of a correctly loaded crystal. 

    T2.1.2 will start at the first clock edge after the supply ramps up. 

    It would be best practice to assert RESET_N until the oscillator has stabilized.  However, it should be noted that power up stabilization timing must still be met before the device will respond to the RESET_N pin. 

    Patrick

  • 0 in reply to Patrick OFarrell
    Intellectual 345 points

    Thanks, Patrick, good answer for me.