TUSB1310A leakage

Hello,

Please send your schematic for review.

Are you connecting a USB device downstream the TUSB1310A?

Can you send a scope capture of DP/DM?

Regards.

Hi,

attached is schematic.

The TX DP and DM  will rise to 500mV when power rails are all up.

Even though I assert the reset signal to low, it does not force this common mode voltage to low or 0V.

Is there a chance phy went into another phy_mode as we left the 2 signal floating?

What is the mode for other setting ? there is no documentation on your datasheet.

Hello,

While you maintain RESET# asserted, the TUSB1310A disables all its internal logic. The voltage measured when the device is held in reset should be induced by the board, can you take a scope capture showing the ramp-up of Vcc and this voltage.

The PHY_MODE terminals have internal PU/PD, so I don't think this is an issue.

They should connect terminals JTAG_TRST to ground, this could be causing the TUSB1310A entering in test mode.

Are they able to establish USB communication?

Regards.

Hi,

I tried force JTAG_RST to ground but it does not help.

attached is the waveform.

I check that during reset, tx_dp & dm is driving a ~22mA current.

After reset is de-asserted, tx_dp &dm is driving a 1.5mA current.

Ch4 = TX_DP

Ch1 = RESETN

Ch3 = 3.3V

Is it possible that PHY has been switched to SATA or PCIe mode if output has common mode voltage?

No, the PHY_MODE internal PU/PD ensure the PHY is in USB mode.

Just to be safe, can you populate an external PU/Pd on these terminals? PHY_MODE1=PD, PHY_MODE0=PU.

Another thing that could be causing is an incorrect assertion of OUT_ENABLE at power-up, this terminal shall never be asserted before the 1.8V rails is valid.

What happens if you connect a USB device downstream?

Are you using the TUSB1310A as a host or device?

Regards.

Unfortunately, the phy_mode signals are not accessible at this moment.

I'm using it as host and system is working but not reliably.

My next question to you is - will there will common mode voltage outpout on TX port if the phy mode is not set to USB3? If so, what is the level?

Hello,

We are still looking into this internally and we'll have feedback by end of this week.

Regards.

Hi,

Do you have any update on the common mode voltage at TX port that I'm seeing?

Do you have /sell any demo PHY board ?

I'l like to purchase one for evaluation.

Hello,

We are having an internal discussion about this Vcm, I'll let you know once we have more information.

We don't sell a demo board for this PHY because it is very implementation specific.

There are some boards that uses our PHY and could help as a reference design http://www.trias-mikro.de/pdfs/asic&assp/prototyping/haps-31-ds.pdf

Here is another platform with this PHY 

http://www.slscorp.com/ip-cores/communication/usb-30-device.html