• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 32 subscribers
  • Views 409 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

XIO2001 and dm648

Kai JI1
Prodigy 20 points
Other Parts Discussed in Thread: XIO2001

Hi,

we have a design which used the xio2001 as the pci-pciE bridge between dm648 and dm8168.  the clock speed in pci side in xio2001 was set to 33Mhz, the design works fine for a long time, but recently when we build more boards, we found some of the boards has data mismatch when senting/receiving data from XIO2001 to dm648 through PCI interface,  the overall chance is not high but still exists, the percentage is around 5%. When we set the clock speed to 66Mhz, this data mismatch seems not happen. I am wondering if the XIO2001 can work with dm648 with 33Mhz PCI clock.   Or there is some points I should pay attention to when XIO2001 is set in 33Mhz PCI clock?

 

Thanks,

JK

 

 

  • 0
    TI__Guru* 76130 points

    Hello,

    The fact that your design has worked before tells me your schematic is correct, nevertheless I would like to review it, can you post it? If not you can post your email I can contact you directly.

    What type of transaction are you doing when the error occur? Upstream read? Downstream write? Burst read?

    Can you send also a PCI register dump of the XIO2001?

    The fact that the implementation works at 66MHz points me to think of a underflow problem.

    Did something changed on your new PCB build?

    Try changing the data payload size.

    Regards.

  • 0 in reply to Elias Villegas M.
    Prodigy 20 points

    Hi,


    we will use the PCI interface to boot the dm648 at the beginning, the data mismatch happens at that booting stage, the entire data transaction at that time is around ~kbytes, and the mismatch also happens in normal data exchange, typically from host to dm648.   I will send you a PCI register dump tomorrow.

    for new PCB build, we didn't change anything in the XIO/PCI/DM648 part, and very puzzled.

    my email address is kai.ji@med.ge.com, I will send you the related schematic.

    Thanks,

    JK

  • 0 in reply to Kai JI1
    TI__Guru* 76130 points

    Hello JK,

    I reviewed the schematic and everything looks correct, there is only one thing, you are connecting SCL and SDA to Vcc thus enabling an external EEPROM interface, the bridge should read that no valid values are at the non-existing EERPOM and load the default values so it is less likely for this to be an issue, however it would be a good practice to pull these lines to ground.

    One thing to check is the layout for the clock signals, the PCB trace going from CLKOUT6 to CLK should be slightly longer than the CLKOUT0 trace.  The load capacitance is also different when operating at 33 or 66, please review Section 7.9 of the XIO2001's datasheet. 

    I also took a quick review of the DM648 datasheet and it should work just fine at 33MHz and 66MHz, make sure you are configuring terminal PCI66 correct.

    The register dump of the XIO2001 looks also correct, however there is something odd on the lspci output as follow:

    For the XIO2001 lspci_33MHz: Status: Cap+  66MHz-

    For the XIO2001 lspci_66MHz: Status: Cap+  66MHz-

    However, for the dm648 lspci_33MHz: Status: Cap-  66MHz-

    and for the dm648 lspc_66MHz: Status: Cap-  66MHz+

    Have you tried with other kernel versions?

    Can you take a scope capture on the PCI bus showing CLKOUT0 and PCI_RST at power up on both cases?

    Regards