DS90UB913Q/DS90UB914Q BIST questions and device behavior without a clock.

Hi Tim,

Somebody is looking into this and will respond shortly.

Regards,

Michael Peffers

High Speed Interface Applications

Thanks for working on this!

I have been working on this more today.  I have a couple of other questions and a couple of comments.

A little background on my questions.  I have an Aptina camera and I need the back channel to configure it before I get a pixel clock.  I prefer to run in "pclock from imager mode" if the serdes can tolerate the jitter, because our software implementation should be identical.  We previously had parallel interface and I2C.

Since I don't have a functional system to send i2c commands to the derserializer / cam yet. I was hoping to see if the linke is solid with internally clocked bist.   I have also tried testing by just sending a 24 MHz oscillator into pclk on the serializer with serializer input data 0.  The serilizer should simply encode this with a 8b/10b code or scramble it or whatever you guys do correct ?  Shouldn't I get a lock light even though I am not toggling hsync and vsysnc?  I never get one.

Also, I don't see anything at the cml monitor on Deserializer pins 38 an 39.  Those pins are sitting at the 1.8 volt supply rail and I have good signal measured with a diff probe at the input coupling caps ahead of the input pins.

Also a comment.  The device doesn't seem to go into bist with the bist pin  unless the bist pin is high before power is brougth up.  If this isn't done, I see a low freq data come out of the deserializer which must be some back channel com.  Is this true?  I also see these low freq data come out of the deserializer if the serilizer is not hooked up.

Also, do you need the RC across the pdn pin on the serializer too?  You seem to have it on the serializer dev kit schematic, which by the way is very hard to read because there is not enough resolution.

I seem to get pass with bist with gpios [1:0] 10 which seems to be a internal bist test at 50MHz.  But no lock light.  The only time I see anything from lock is slight flicker of pass and lock with gpio[1:0] 11 (12.5MHz) bist test.

I also have multiple eye patterns that I have caputred for reference.

Thanks again!

Tim

Hey Tim,

Are you getting lock when you are not in BIST? You should be able to get lock without a pclk.  I have tried to answer most of your questions below.  We do have a reference design for the 913A with an Aptina camera module posted here:http://www.ti.com/tool/tida-00098.

Is it ok to have serializer io at 2.8 and deserializer io at 3.3V ? 

Yes

I am running the camera with the imager clock as source.
If no camera imager clock is there I2C through back channel?

Yes, when there is no pclk the link should be locked to the 913A's internal generator allowing I2C through the back channel

If no imager clock does serializer gernerate one?

Yes

In bist mode if there is no imager clock does the serializer generate one?

You can select the clock source for bist from the table below

Can the bist be initiated via hardware bist enable on the deserializer?

Yes, setting the pin high will enable BIST.

Does back channel tell the serializer to enter bist mode?

Yes

Can bist test be initated solely with a jumper on the bist pin on the deserializer to test the link?  I would prefer no software required to see if link is good.

Yes

Should pll lock light go on in bist mode ?

Yes, the link must be locked for bist to work.

If all zero data bist should work fine, correct?

Yes

Is mode ignored in bist?  I have the bist set at 50 \MHz gpio\[1:0]=10, line rate is 695.41MHz.
Bit rate doesn't seem to change between bist gpio\[1:0]=10 (50Mhz) and gpio\[1:0]=01 (25MHz) as a function of bist frequency.  But the eye closes for bist 01.  Why would that be ?

Line rate bist 12.5MHz is 353.6MHz
Finally, I have some eye patterns to discuss.  I am not passing bist at 25MHz and 12.5MHz.  I am set up for imager (pclk) as clock source.  I am not providing a imager clock during the bist tests.   I get solid pass at 50MHz but I never see a lock light

Are you getting lock when you are not in BIST?

Also, I don't see anything at the cml monitor on Deserializer pins 38 an 39.  Those pins are sitting at the 1.8 volt supply rail and I have good signal measured with a diff probe at the input coupling caps ahead of the input pins.

The CML output is not enabled by default. You have to set the deserializer reg 0x3F to 0x00.

Also a comment.  The device doesn't seem to go into bist with the bist pin  unless the bist pin is high before power is brougth up.  If this isn't done, I see a low freq data come out of the deserializer which must be some back channel com.  Is this true?  I also see these low freq data come out of the deserializer if the serilizer is not hooked up

If you are configuing by pin strapping you will need to toggle PDB or cycle power for the changes to take effect.  If you set the device into bist using I2C then you do not need to cycle power.

Also, do you need the RC across the pdn pin on the serializer too?  You seem to have it on the serializer dev kit schematic, which by the way is very hard to read because there is not enough resolution.

Yes

I never see a lock.  Only a flicker with a lock with GPIO [0:1] 1 1 which in the old data sheet was 12.5MHz in 12 bit low frequency mode. 

I have uploaded bist mode with GPIO (1 1) 12.5MHz 12bit mode low freq mode, 25MHz 12 bit low freq mode and 50 MHz low freq mode.

Bist 25 MHz:

Bist 12.5 MHz

Hi Tim,

Are you willing to send me your schematic?  Also what type of cable are you using and what is the length?

m-mellitt@ti.com

Regards,

Mike

Hi Mike,

I don't see any problem sending the serializer/deserializer portion of the schematic.  I am double checking though.  As soon as I get a yes I'll send it.

Thanks,

Tim