Gilbert,
The answers are listed below.
-Atul
Hello,
One of my customers is developing with our TLK3132 :
They have some questions that I submit you :
1) Is it possible to activate the Rx FIFO / CTC function in the SERDES reception block without activate the 10b-8b decoding function ?
If yes , how to do it ?
No, it cannot be done without 1000Base-X PCS mode enabled.
2) Questions concerning
the RCLK and RXCLK clocks :
In the figure 2.6 Detailled 1000Base-X Core Block Diagram page 16 of the TLK3132 DS , we see 2 times the RXCLK signal :
> The first RXCLK derives from the RCLK that comes from the serial input flow ( FIFO inactive)
> The second RXCLK derives from the 8b/10 Decoding block --> Question : Does this clock is realigned in term of phase on the REFCLK_P,N ( FIFO active) or does it comes from the serial input flow ( FIFO inactive) ?
Please see if attached picture helps. It’s for 3134, but is similar for 3132.
3) Can we generate the DDR 10 (mode TBID, sortie RXCLK[1:0] ) flow in
phase/frequency with the REFCLK_P,N ?
No, they are not related.
4) We use the character Comma decoding function on the receiver , from the
ARINC818/FIBRE CHANNEL 3.1875Gbit/s flow formed by the IDLE
(K28.5/D21.4/D21.5/D21.5) words.
Questions : a) The status SYNC bit of the SERDES_RX0_STATUS
register is not stable , Could you please explain us how does the character
Comma decoder work on the TLK3132 ?
The Sync bit indicates if the state machine implemented in Clause 36 of IEEE802.3 is in the synchronization state. It is likely you have high bit errors causing loss of synchronization.
b) Does the SYNC bit shift to
'1' for the K28.5 and '0' for the Dxx.x ?
It shifts to one when the channel has received enough comma characters in absence of 8b/10b decode errors.
State machine shown below as reference (ignore the box talking about hysteresis, it’s not in 3132):
Many Thanks for your support
Best Regards
Gilbert