Hi to all.
I develop ethernet driver for my switch board. I have some problem with PHY level based on DP83620.
Now I have a 50 MHz at TX_CLK and RX_CLK, but 25MHz at CLK_OUT instead of 50MHz RMII Reference clock in RMII Master Mode((((((
Device is configured by strap options for RMII Master Mode. Primary Clock Reference Input is 25 MHz.
Help me, plz!!!