Hi,
I have been having an issue with transmitting data using the DP83865 PHY. I am running in 100 Mbps mode and have been able to receive data into a FPGA. Since the data comes in with the LSB first, I swap nibbles for the Ethernet block in the FPGA. The data then makes it through the Ethernet block without issue. After receiving an ARP from the computer, I can see the FPGA transmit an ARP back out on the TX[3:0] lines. I format this data the same as the receive data was coming in. However, I never see a response to the ARP from the computer when monitoring traffic using wireshark. Below is an example of received data and what I convert it to:
C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 CD => 55 55 55 55 55 55 55 D5
So when I send data out, I flip the LSB and MSB since that is how it is received into the FPGA, as such:
55 55 55 55 55 55 55 D5 =>05 05 05 05 05 05 05 05 05 05 05 05 05 05 05 0D
Could you please let me know if my assumption on flipping the data before transmitted is flawed or if you have any other tips as to what I may be able to do to correct this problem?
Thanks
