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Some questions regarding TUSB73x0

Alexander Alioshyn
Prodigy 170 points

Hello!

I am designing a SMARC carrier board. Almost everything is clear with the TUSB73x0 implementation except for:

1. In SLLU149B on page 29 it is said that the pull-up resistor should be 10k while in SLLZ067B it is said that 1.5k is ok and the tweaking may be required. So, what is the best initial value for that resistor?

2. In SLLZ067B it is also said that the WAKE# or CLKREQ# requires a pull-up and that both of them do require a 0.001uF cap to ground. Is that correct? If I want to implement an additional FET as in SLLU149B, should I add one pull-up only for WAKE# or I should provide pull-ups for both signals? The recomendations for non-english speakers are rather confusing.

3. I have an EVM board. Traceroute recomendations say that I should route USB3.0_SS pairs far from each other. In my design it is quite difficult because I want to use the four layer stack-up and the TUSB73x0 is located above the GND surface. I can not provide the unsplit GND plane on the other inner layer. Can I route the SS pairs on the same layer at which the chip is soldered? I can provide large distances between SS far from the ic but near it the clearence will be quite small. Were there any simulations with the SS signals routed in an escape manner without using of vias to another layer? How bad will be the signal degradation? Unfortunatelly I can not do any simulations right now.

Thanks in advance!

  • 0
    TI__Mastermind 20820 points

    Hi Alex,


    I am moving this post over to the CCI - Consumer and Computing forum as that group supports this part.

    Regards,

    Michael Peffers

    High Speed Interface Applications

  • 0
    TI__Mastermind 36085 points

    Hello Alexander,

        Here you go the answers to your questions:

         1 and 2.-  Follow the recommendation  the "TUSB73x0 Board Design and Layout Guidelines" (sllu149c, http://www.ti.com/lit/ug/sllu149c/sllu149c.pdf). You must follow the recommendations on the errata only in the case that the implementation behaves as described by the errata. this scenario is valid only if the rising time of WAKE# or CLKREQ# is too fast (lower than 1.5us).

        3) Your layout plans seems to be OK, and may work fine, just try to spread the USB3 traces within the possible shorter distance, you can use the EVM layout as a reference, where you can see the USB3 traces on the bottom layer.

    Best regards,

    Diego.