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SN65LV1xxx Margin and Behavior

Reagan Revisore
Expert 4225 points

Hi all,

We're working with an SN65LV1224 and SN65LV1023, and have a couple of related questions which are outlined below. Any answers and insight that could be offered would be greatly appreciated!

1) An input jitter specification is levied on TClk, but no requirement is placed on RefClk.

Does this mean that the PLL inside the reciever only uses RefClk to more quickly converge on TClk? (RefClk jitter is unimportant as long as the clock does not drift by more than +/-100ppm)

2) Do TClk and RefClk have to be the same speed and if so, how does a frequency offset affect the link margin?

3) Does the transmitter's output jitter decrease if TClk Jitter is better than required? (if so, what is the intrinsic jitter of the PLL?)

4)Deserializer noise margin is specified as 3680ps(10MHz) - 540ps (66MHz), does the margin scale linearly with frequency? (38MHz - 2110ps?)

5) Are there any hard numbers for margin? (Allowing me to allocate margin to transmission line noise)

6) Deterministic and Random jitter are broken out for the serializer, is the 80ps deviation between operation at 10MHz and 66MHz scale linearly with the frequency change?

  • 0
    TI__Mastermind 20820 points

    Hi Reagan,

    1. The spec on REFCLK is +/-100ppm of the incoming data rate so that the PLL can sync to the data.

    2. Yes the TCLK and REFCLK should be the same speed. If they are different then the receiver will not recover the data properly which will severely effect your link margin.

    3. The output jitter of the TCLK is specified in the data sheet on page 10 as TDJIT(MAX) = 230ps and TRJIT(MAX) = 19ps.

    4. It is close to linear but may not be 100%.

    5. All the data for allocating your noise margin is listed in the data sheet.

    6. It is close to linear but may not be 100%.

    Regards,

    Michael Peffers

    High Speed Interface Applications