Regarding timing and logic level info of TUSB1211A1ZRQ

Hello Kishore,

    Could you be more specific regarding the information you need?

Best regards,

Diego.

Hi Diego,

Please provide the below informations.

1. Setup Time required for DATA and CMD (STP) in TUSB1211A1ZRQ

2. Output frequency accuracy of TUSB1211A1ZRQ in the CLOCK pin.

3. Minimum Input voltage that TUSB1211A1ZRQ recognises as High Level (VIH min) and Maximum Input  Voltage that TUSB1211A1ZRQ recognises as Low Level (VIL max)

Regards,

Kishore Kumar

Hello Kishore,

   These are the ULPI timing characteristics:

RESET_N input pin timing spec:

tw(POR) Internal power-on reset pulse width 0.2 µs
tw(RESET)External RESET_N pulse width: 8 CLOCK cycles (Applied to external RESET_N pin when CLOCK is toggling.)

The output accuracy is highly dependent on the input clock on REFCLK and shall be similar to it.

The electrical characteristics for the digital inputs are the following:

For: CLOCK, STP, NXT, DIR, DATA[7:0]

V_{OL_MAX}:0.45V            V_{OH_MIN}:V_DDIO-0.45V

V_{IL_MAX}:0.35*V_DDIO    V_{IH_MIN}:0.65*V_DDIO

FREQ_MAX:30 MHz      LOAD_MAX: 10pF

RISETIME_MAX:1ns      FALLTIME_MAX:1ns

FREQ_MAX(only for CLOCK): 60MHz

For: CS, CFG, RESETB input pins

VIL  0.35 * V_DDIO
VIH 0.65*V_DDIO

Best regards,

Diego.

Hi Diego,

Thanks for sharing the timing specification.

1. As per the ULPI specification timing (shared by you), Setup Time should have a maximum value of 6 ns. Our captured setup time (of DATA0) is 13.0337 ns (Please refer below scope shot). As per the spec it is failing, but functionality (ULPI communication between Link and PHY) is met. We hope the setup time required by TUSB1211A1ZRQ, to properly recognize data should be given as minimum 6 ns. Kindly clarify.

2. In the REFCLK electrical characteristics, we could see 'REFCLK input integrated jitter' should be maximum 600 ps rms. Kindly let us know the range of frequencies over which the 'Phase Jitter' has to be computed.

3. In the information provided, it is mentioned that 'RISETIME_MAX:1ns      FALLTIME_MAX:1ns'. We hope it is the output spec of TUSB1211A1ZRQ. Kindly clarify.

Regards,

Kishore Kumar

Hi Diego,

Thanks for your response. Please clarify the below mentioned points.

1. We believe that RISETIM_MAX and FALLTIME_MAX limit values, provided above, are for the output signals of the USB transceiver. If so, then what is the RISETIME_MAX and FALLTIME_MAX  limit values for the input signals (REFCLK, STP, DATA[7:0]) ?

2. For REFCLK, Shall I take VIL_MAX and VIH_MIN limit values from the above mail?. If not, then what are the electrical characteristics (VIL_MAX and VIH_MIN) of REFCLK?

Regards,

Kishore  kumar

Hello Kishore,

   To clarify the information:

    1) Your assumption is correct, the setup time is a minimum (sorry for the mistake).

    2) First I need to know the implemented clock mode. Unfortunately the ULPI specification does not provides jitter requirements for this stage.

    3) The rise and fall times are output specs, don't worry about it.

Best regards,

Diego.

Hello Kishore,

    There are no input rise and fall time specs for the ULPI interface, however you can use the output specs as a reference.

    Yes your assumption is correct,  you can take the previous values of VIL_MAX and VIH_MIN limit values from above (V_{IL_MAX}:0.35*V_DDIO    V_{IH_MIN}:0.65*V_DDIO).

Best regards,

Diego. 

Hi Diego,

Thanks for your clarification.

1. We use "ULPI output Clock Configuaration" with REFCLK frequency 19.2MHz (CFG pin is tied to GND). 

2. As I've previously mentioned, we could see a parameter named "REFCLK input integrated jitter" in TUSB1211A1ZRQ datasheet (refer below snap shot). You've previously clarified that the term actually means "Phase Jitter". Phase Jitter is usually computed from Phase Noise which in turn is computed between a frequency range. Kindly let us know the frequency range over which phase jitter has to be computed.

3. Kindly let us know if any best known method is available for computing Phase Jitter (like the range of frequencies over which it has to be computed, nominal noise floor of the scope, suggested probes (single ended low input impedance/high input impedance, differential, etc), total population/clock cycles to be considered,etc).

Regards,

Kishore Kumar

Hi Diego,

Thanks for your appropriate response.

Regards,

Kishore Kumar