Regarding REFCLK integrated jitter in TUSB1211A1ZRQ

Kishore Kumar3

There is a parameter named "Input Integrated Jitter" for REFCLK in TUSB1211A1ZRQ. Believe it is Period RMS jitter. Please confirm.

over 11 years ago

0 Diego Cortes over 11 years ago

TI__Mastermind 36085 points

Hello Kishore,

the input integrated jitter is referring to the Phase Jitter (ps RMS). here you go some guidelines to understand this specification:

http://www.maximintegrated.com/app-notes/index.mvp/id/3359
http://www.eetimes.com/document.asp?doc_id=1277196\

Best regards,

Diego.

0 Kishore Kumar3 over 11 years ago in reply to Diego Cortes

Prodigy 130 points

Hi Diego,

Thanks for your immediate response.

We've measured period jitter of REFCLK using Tektronix 12.5GHz scope(DSA71254B) using DPOJET application.

Measured RMS value is around 30ps. Value specified in "TUSB1211A1ZRQ" datsheet for "REFCLK input integrated jitter" is 600ps. Can I say that my REFCLK jitter is within limits?

Can we correlate phase jitter(RMS) with period jitter(RMS)?

Regards,

Kishore Kumar

0 Diego Cortes over 11 years ago in reply to Kishore Kumar3

TI__Mastermind 36085 points

Hello Kishore,

Of course you are within the spec. Regarding the correlation, I think it is possible however I am not sure how to correlate both values properly.

Best regards,

Diego.

0 Kishore Kumar3 over 11 years ago in reply to Diego Cortes

Prodigy 130 points

Hi Diego,

Thanks for your confirmation.

Our REFCLK frequency is toggling between 19.18471MHz to 19.2131MHz (CFG pin is tied to ground in

TUSB1211A1ZRQ). Measured jiter value is around 30ps and it is very well within the range.

The output CLOCK generated by TUSB1211A1ZRQ, is toggling between 59.8045MHz and 60.1814MHz in steady state. But in ULPI specification, the Steady state frequency is mentioned as 59.97MHz to 60.03MHz, measured value is out of this range.

Kindly clarify the reason why the output CLOCK frequency is not within limits.

Regards,

Kishore Kumar

0 Diego Cortes over 11 years ago in reply to Kishore Kumar3

TI__Mastermind 36085 points

Hello Kishore,

Please attach an scope capture of the input and output clock, I would like to review them.

Best regards,

Diego.

0 Kishore Kumar3 over 11 years ago in reply to Diego Cortes

Prodigy 130 points

Hi Diego,

Please find the below scope shots.

REFCLK Input:

7585.USB_ULPI_REFCLK_Jitter.zip

CLOCK Output:

As per the ULPI specification, the OUTPUT clock should get into steady state (Frequency lies between 59.97MHz and 60.03MHz ) within 1.4ms from first transtion. But in our case the clock frequency is not within that range (Toggles between 59.8045MHz and 60.1814MHz).

The clock frequency is not within the steady state limits even after 10ms (it is not getting stable even after minutes) from first transition.

Kindly clarify.

Regards,

Kishore Kumar

0 Kishore Kumar3 over 11 years ago in reply to Kishore Kumar3

Prodigy 130 points

Hi Diego,

Gentle Reminder:

Please respond to the above query.

Regards,

Kishore Kumar

0 Diego Cortes over 11 years ago in reply to Kishore Kumar3

TI__Mastermind 36085 points

Hello Kishore,

I am moving this issue to an internal discussion, in order to accelerate the solving process. I will provide a feedback as soon as I get any answer.

best regards,

Diego.

0 Kishore Kumar3 over 11 years ago in reply to Diego Cortes

Prodigy 130 points

Hi Diego,

Is there any updates on the above issue?

If so kindly let us know.

Thanks and Regards,

Kishore Kumar

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Regarding REFCLK integrated jitter in TUSB1211A1ZRQ