DP83640 MDIO issue

Charles Hermann

Other Parts Discussed in Thread: DP83640

Hello:

I am having an intermittent communication issue with the DP83640 phy and a SPEAr320 processor running embedded Linux. 25% of the time the MDIO communication fails and the phy is not detected. I suspected timing and added a 18pF cap to the MDIO line and gnd as a test and this vastly improved reliability. There is nothing in the documentation to suggest that MDIO and MDC should be routed as trace length matched pairs but the other interface does not have this problem and the traces are routed very closely together while the problem interface has the two signals taking different paths. quite curious. Is this a requirement that I simply don't know about.

Regards,

over 11 years ago

0 Patrick OFarrell over 11 years ago

TI__Mastermind 31600 points

There is no specific requirement to route MDIO and MDC as a trace length matched pair. What are the approximate trace lengths of the MDIO and MDC signals?

What does it mean that 25% of the time the communication fails? Does it occur for 25% of the register accesses on a given board? Or does this behavior occur for 100% of the register accesses for 25% of the boards tested? I am trying to get a feel for the consistency of the described behavior.

Patrick

0 Charles Hermann over 11 years ago in reply to Patrick OFarrell

Prodigy 40 points

I only have the one board available as this is an early prototype. On this board 25% of the register accesses seem to fail. Greatly improved simply by adding a 18pF cap to gnd on the MDIO line. I cannot get a length as these boards were designed by someone else and while I have the PADS files I am currently working out a PADS licensing issue. I will install the reader today and see if I can take a closer look.

Thanks,

0 Charles Hermann over 11 years ago in reply to Charles Hermann

Prodigy 40 points

Yeah, I may have spoken too soon. I put a scope on the signal and It appears that the MDIO signal is ringing like a bell the clock looks clean however. MDIO looks a lot better with the cap on the line. I will have to clean this issue up before I do anything else. I will open another thread if there is a problem after I solve this issue

Regards,

0 Patrick OFarrell over 11 years ago in reply to Charles Hermann

TI__Mastermind 31600 points

With your approval, I will close this thread as a signal integrity issue on the register interface. We can address any future questions on a new thread.

Patrick

0 Charles Hermann over 11 years ago in reply to Patrick OFarrell

Prodigy 40 points

Agreed.

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DP83640 MDIO issue