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DS90CF384

eli
Guru 13485 points
Other Parts Discussed in Thread: DS90CF384, DS92LV2412, DS92LV2411

customer identified that the major cause of their EMI problems comes from the LVDS to RGB IC DS90CF384

Can you find a replacement with spread spectrum capability?

  • 0
    TI__Mastermind 20820 points

    Hi Eli,


    Somebody is looking into this and will respond shortly.

    Regards,

    Michael Peffers

    High Speed Interface Applications

  • 0 in reply to Michael Peffers
    Guru 13485 points

    Hi Michael,

    Thanks.

    If needed customer is ready for redesign his board, to use other recommended device/solution.

    B.regards

    Eli

  • 0
    TI__Mastermind 29655 points

    Hi Eli,

    The DS90CF384 is an FPD I generation device, and unfortunately we do not have any LVDS-RGB ICs in our portfolio that can perform the spread spectrum clock generator (SSCG) function and is a drop-in replacement for the DS90CF384.

    I would advise if SSC is a major concern and a board redesign is possible that you upgrade to Channel Link II and try a device like the DS92LV2411/DS92LV2412, which also supports 24-bit Color. However, you will need to use a different input interface, as all the lines are serialized onto one CML differential pair for Channel LInk II.

    Thanks,

    Michael

  • 0 in reply to Michael Lu (Santa Clara)
    Guru 13485 points

    Hi Michael,

    SSC is not a must. looking for any  solution  that will not have EMI problem.

    B.regards

    Eli

  • 0 in reply to eli
    TI__Mastermind 29655 points

    Hi Eli,

    FPD Link I devices do not have much capability to assist in minimizing EMI like those seen in the later generation devices. All it offers is the low LVDS voltage swing, which helps reduce EMI when compared with RS-422, PECL, and TTL.

    You will find more particular features to reduce EMI in the next generation of Ser/Des products (Channel Link II or III). For example, to reduce EMI in the DS92LV2411/DS92LV2412, the deserializer has SSCG, output slew rate control, and data randomization/scrambling. 

    Thanks,

    Michael

  • 0 in reply to Michael Lu (Santa Clara)
    TI__Expert 3050 points

    Hi Eli,

    Due to the nature of LVDS signaling, FPD-Link I devices are typically low EMI products if the PCB is designed properly. Here are some typical high speed design practices to reduce EMI:

    • tightly couple differential traces
    • route high speed or toggling traces on inner layers
    • ensure that vias for high speed or toggling signal traces have adjacent return vias that simply provide a constant path to ground
    • minimize via stub length, consider back drilling vias depending on board stack up/routing and data rate
    • ensure that the high speed traces have constant trace spacing/routing 
    • use shielded cables and connectors
    • minimize differential +/- skew, intra-pair skew
    • if you have dc balancing in your system, consider using common mode chokes on the differential traces
    • consider employing series termination resistors, typically 10-33 ohms, on the LVCMOS I/Os

    Mike Wolfe

    DPS APPS / SVA