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PCA9515A I2C address translation

Madhuri Akkenepalli
Expert 1215 points
Other Parts Discussed in Thread: PCA9515A, TCA9543A

In order to translate the I2C address of the CXP transceiver from 1010000x (A0/A1) to 1011000x (B0/B1), I would like to do the following:

 

  1. Connect the SDA wire from the main SDA/SCL I2C bus to the CXP I2C bus wire, CXP_SDA, through the buffer PCA9515A.
  2. Connect the main SDA/SCL I2C bus to a CPLD.
  3. Connect one CPLD output to the EN pin of the PCA9515A, another CPLD output (open-collector) – to the CHP_SDA .
  4. Make the CPLD check the first 3 bits of the I2C address; if they equal 101, disable the PCA9515A for one SCL clock period and set CXP_SDA low for one SCL clock period from the CPLD. As a result, the fourth address bit of the CXP_SDA (but not of the SDA) will be 0 if the first 3 address bits were 101 (i.e., when the bus master sends the address 1011xxxx, the devices on the main bus will see the address 1011xxxx, but the address on the bus CXP_SDA will be 1010xxxx).

 

I would like to know from you whether it will hurt anything if I disable the PCA9515A for one clock period on-the-fly (when the bus is active) ?

If for some reason you do not recommend to use the PCA9515A this way, any alternative proposals would also be very helpful.

  • 0
    TI__Mastermind 30280 points

    Madhuri,

    Can you share a schematic of the proposed application or a detailed block diagram?

    I am afraid if I draw my own block diagram that I may miss some important information, and I would like to ensure the proposed application is well understood before confirming the design or suggesting an alternative part.

    Thanks,

    Brian

  • 0 in reply to Brian Berner
    Expert 1215 points

    Hi Brain,


    Thanks for your support. Please find the block diagram attached that shows the I2C address translation.


    Please let me know if this helps.

    regards

    Madhuri

    I2C_address_translator.pdf
  • 0 in reply to Madhuri Akkenepalli
    Expert 1215 points

    Hi Brain,

    Please advise if you had a chance to look at the block diagram. This is critical information needed to move forward on our design. Please let me know of the options.

    regards,

    Madhuri

  • 0 in reply to Madhuri Akkenepalli
    TI__Mastermind 30280 points

    Madhuri,

    It appears that you are trying to resolve an I2C address conflict in a way that has not been validated, and the timing conditions needed to make this happen may be difficult to meet (especially if the I2C bus is operating at 400 kHz).

    Can you consider using a TCA9543A (2-channel I2C mux) to resolve this address conflict?

    You can enable channel 0 when you want to communicate with the EEPROM and enable channel 1 when you want to communicate with the CXP slave.

  • 0 in reply to Brian Berner
    Expert 1215 points

    We cannot use I2C multiplexers because the EEPROM is located directly on the main bus and is out of reach. Can your please give me the details of your concern about using PCA9515A, and what timing conditions you are talking about.

    Thanks

    Madhuri

  • 0 in reply to Madhuri Akkenepalli
    TI__Mastermind 30280 points

    Madhuri,

    The timing concerns I am talking about are whether or not the CPLD-->Enable circuitry will be fast enough to meet the "Setup time" and "Hold time" requirements on page 5 of the datasheet and of the I2C specification.

    Will Enable go low and will the output of the PCA9515A be disabled in a shorter period of time than the Setup time?

    Will Enable go high and will the output of the PCA9515A be enabled in a shorter period of time than the Setup time?

    And will the CPLD hold Enable high or low long enough to meet the Hold time requirement.

    If there is an internal clock in the CPLD you may be able to control this timing.

    -Brian