DS92LV16 SYNC pulse width

Hi Toshi-san,

The SYNC input is an LVCMOS/LVTTL level signal that will cause the serializer to ignore data inputs and send a SYNC pattern in order to regain LOCK if the SYNC input is high for 6 TCLK cycles. I believe the 5 or 6 * tTCP pulse width you are seeing is the required amount of time the SYNC pulse must be held high in order to initiate a serializer SYNC pattern output. Once the SYNC pin is held high for at least this amount of time, all receiver input data is ignored until the SYNC pin is pulled low again. This is also why it is recommended to resend the data that was present in the 5-6 TCLK cycles before the SYNC pattern was started.

The /LOCK output signal is actually a recommended control for applying directly to the SYNC input so that the SYNC pattern is only triggered when loss of lock occurs. Please see p. 13 of the datasheet, highlighted below:

Thanks,

Michael