Driving SN65LVDS20 with single Ended LVCMOS 3.3V signal

Hi Niels,

I imagine that this would work, I have tested this type of operation with similar IC's in the past. Before I commit to it though I would like to do some bench testing and collect some test data off of the EVM. What data rate are you interest in for the LVCMOS signal?

Regards,

Michael Peffers

High Speed Interface Applications

Hi Micheal,

the Data rate ranges from DC to 20MHz.

By the way, the LVCMOS output driving the SN65LVDS20's A input will be a SN74LVC1G10 from TI. :-)

Regards,
Niels

Hi Neils,

Thank you for the information. I have an engineer that is going to test it this afternoon and he will reply either tonight or tomorrow morning. I will him spot check the device at 3 frequencies (min, max and somewhere in between).

Regards,

Michael Peffers

High Speed Interface Applications

Hi Niels,

The SN65LVDS20 did not operate well in this fashion. The duty cycle did not look right so I suspect that one or both of the transistors went into saturation and the device could not handle it. If we look closer at the Vid spec in the data sheet we violate the 1V maximum by switching with the LVCMOS levels.

We do have the SN65LVDS1 which is made for LVTTL/LVCMOS to LVDS translation. Please take a look at this part and let me know if you have any questions?

Michael,

sorry for the delay, we had a long weekend here in Germany.

I can't use the SN65LVDS1, since I need the Enable-Feature of the SN65LVDS20.
Do you have any other suggestions? Some way to adapt the LVCOMS voltage level?

Regards,
Niels

Niels,

the attached additional circuit would simulate the Enable function, so you could use the SN65LVDS1.

Dependent on the voltage level at the FET-Gate your device is powered on or off (gate low = on, gate high = off).

Best regards

Markus Zehendner

Hello Markus,

good idea. But depending on the value of "R", it may waste a lot of power in the disabled state.

In the data sheet of the SN65LVDS1 I can see that Icc is 8mA, and the power supply may be as low as 2.4V. I will use a 3.3V Supply, which allows R = 112 Ohm in the first approach. This series resistor will lead to an "unstable" power supply seen by the SN65LVDS1 when Icc changes during operation. Will this influence the AC-performance of the SN65LVDS1?

Regards,
Niels

Hi Niels,

the requirements for the resistor are on one hand, being able to supply 8mA, but on the other hand it has to be a high enough value to limit the current to a certain degree, when the FET is on. The addition of a second resistor on the source side can make things easier. R2 will limit the current, when the FET is on. R1 then can be a much smaller value and will dissipate less power overall.

You also have to consider that the SN65LVDS1 will only be ready for transmission after the time T = R1*C. If you wait for the supply voltage to be established on C, there will be no "unstable power".

Best regards

Markus Zehendner