SN75DP130DS power sequencing

D. Johnson

Other Parts Discussed in Thread: DP130DSEVM

Customer has some concerns regarding power up / down sequencing.

Figure 5 (below) of the data sheet indicates VCC must be delayed by 10us or more, reset is deasserted >100us after VCC valid. Power down side looks like, reset, then VCC, then Vddd. Evaluation hardware (DP130DSEVM) does not appear to have any power sequencing or much in the way of a reset circuit (simple cap)

Question(s) –

Is the reset before power down a requirement?

Is the VCC before Vddd power down sequence a requirement?

Thanks

Dave Johnson

over 11 years ago

0 Diego Cortes over 11 years ago

TI__Mastermind 36085 points

Hello Dave,

The datasheet shows the recommended power down sequence, however you should don't have any issue if you change the power off sequence, as long as you respect the power up sequence.

Best regards,

Diego.

0 D. Johnson over 11 years ago in reply to Diego Cortes

Intellectual 700 points

Just to clarify

It is OK to Ignore reset assertion before power down.
It is OK to Ignore VCC off before VDDD during power down.
VDDD must be stable 10uS before VCC ramp up during power up. This would mean coincident power up of VDDD and VCC is not allowed.

Thanks

Dave

0 Diego Cortes over 11 years ago in reply to D. Johnson

TI__Mastermind 36085 points

Hello Dave,

your assumptions are correct.

Regards,

Diego.

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SN75DP130DS power sequencing